A Simulation Study Of Interfacial Properties Of High-K/GaAs MOS

Ga As MOSFET with higk-k gate dielectric combine the advantage of high mobility of Ga As and low leakage current of high-k gate dielectric, which is expected to become a new way for the continuation of Moore's Law. However, there are many interface traps between high-k dielectric and Ga As. What's more, the effect of interface trap on the capacitance and electrical properties of high-k/Ga As MOS is lack of awareness, which is seriously hinder the application of the structure of high-k/Ga As. Therefore, a deep exploration of the influence mechanism of interface trap on electrical properties can explain the important phenomenon in experiment but also can provide the theory evidence for fabrication of high-k/Ga As MOSFET.For the material characteristics and physical parameters of high-k/Ga As MOS such as interface trap, band structure of Ga As, energy quantization, carrier distribution and transport mechanism, the applicability of the model of trap, mobility, generation-recombination, quantum, nonparabola and multivalley to device characteristics is discussed. Besides, the key parameter of models is confirmed. On this basis, the effect of interface degradation on mobility of electron and that of quantum on capacitance are emphatically explored.The effect of interface trap with different density, different position in forbidden band on the capacitance of high-k/Ga As MOS is explored at different frequency. Besides, phenomena of bump in the inversion region and the frequency scattering of n-type Ga As MOS is more obvious than p-type Ga As MOS is explained. What's more, the results of simulation and experiment C-V curves are almost equal to in EOT, flat band voltage and the density of interface trap, which verifies the validity of the numerical simulation model of high-k/Ga As.Device characteristics of high-k/Ga As MOSEFT is also simulated by using the simulation model. It is found that interface trap can increase the threshold voltage and reduce the electron mobility and transconductance by the simulation. Furthermore, the effect of different interface trap density is also compared with. It is found that, the effect of interface trap on electrical properties is small when the interface trap density is less than 1×1012 cm-2e V-1. When the interface trap density is 1×1012 cm-2e V-1, the threshold voltage increases by 0.2V and the maximum reduction of electron mobility is 500ms/mm. Therefore, when the the interface trap density is larger than 1×1012 cm-2e V-1, the degeneration of electrical properties caused by interface trap density is considerably serious. The effect of same interface trap density on P-type Ga As MOSFET and P-type In_0.53Ga_0.47 As MOSFET is compared with. The degeneration of electrical properties of P-type In_0.53Ga_0.47 As MOSFET caused by the same interface trap density is smaller than that of P-type Ga As MOSFET due to its smaller bandgap and energy disparity between the Charge-Neutrality-Level?CNL? and the bottom of conduction band. Therefore, In_0.53Ga_0.47 As is a great potential substrate of MOSFET.