Interfacial Structures And Electrical Properties Of Atomic Layer Deposited High-k Dielectric Thin Films On Ⅲ-Ⅴ And Ge Semiconductors

Si-based CMOS devices have been successfully scaling down for decades to meet Moore’s Law. With higher operating frequency and larger integration density in a single chip, the power density is becoming a more and more serious issue. Therefore, power constraints are the major concern for future transistor engineering. Power density is proportional to the operating voltage squared, indicating power density can be greatly reduced by using low voltage. Ge and III-V materials are the promising solutions because they inherently have very high carrier velocity at low electric field, which means the transistors can maintain high performance at low operating voltage, using reduced power. However, it also poses many difficult challenges and perhaps the most difficult and long-standing problem is passivation of the defects that inevitably form between deposited gate insulators and channel materials.In this thesis, I mainly focus on the interface studies of atomic-layer-deposited (ALD) high k gate dielectrics on high mobility materials such as GaAs and InGaAs, for n-channels and Ge for p-channels. The surface passivation, interface structure, band alignments, and electrical properties were investigated systematically. The meaningful results in this work are following:1. First, the effect of (NH4)2S and (NH4)2SeO3 passivation on the structural and electronic properties of the Al2O3/GaAs(111)A interface is investigated. By using multi-frequency capacitance-voltage (C-V) and conductance-voltage (G-V) approaches, we determine the interface trap density (Dit)-its energy level within the semiconductor bandgap. Electrical properties show that selenium passivation can effectively lower Dit within the lower half of the GaAs band gap than sulfur passivation, while sulfur passivation is more effective in reducing the gap states in the upper half region of the gap. To further reduce the Dit of oxide/GaAs gate stacks, high-quality epitaxial La1.1Y0.9O3, La2O3 thin films are achieved by an ex situ ALD process, and GaAs MOS capacitors made from this epitaxial structure show very good interface quality with small frequency dispersion and D;t. In particular, the La2O3/GaAs interface, which has a lattice mismatch of only 0.04%, shows very low Dit in the GaAs bandgap, below 3×1011 cm-2 eV-1 near the conduction band edge. We also find that a low-frequency plateau in conductance spectra of high-quality atomic-layer-epitaxial high-k/GaAs MOS capacitors. A new interpretation for the signals has been proposed for the first time at III-V MOS interface studies. By using the tunneling model to incorporate the border traps, we obtain good fitting to the experimental data. The high-frequency peak and width values in the conductance spectrum are attributed to interface traps and surface potential fluctuation, whereas the low-frequency plateau can be ascribed to the contribution from border traps. The Nbt at the energy level E-Ev= 0.91 eV of the amorphous Al2O3, epitaxial La1.1Y0.9O3, and epitaxial La2O3 films are 2.0×1020,4.7×1019, and 6.1 ×1018 cm-3·eV-1, respectively.2. We report on the electrical characteristics of Al2O3 gate dielectrics deposited on n-In0.75Ga0.25As by ALD, after in-situ ammonia gas surface cleaning procedures. It is shown that ammonia gas passivation prior to growth damages to the semiconductor surface and increase the Dit, up to 3.5×1013 cm-2·eV-1 near midgap. The effect of forming gas (4% H2+ 96% N2) annealing (FGA) on the electrical properties of A12O3 gate dielectric films grown by ALD on Ino.75Gao.25As substrates has been systematically investigated. It is found that 350℃ FGA for 30 min is more effective to reduce the interface states down to a minimum Dit value of 3.7×1011 cm-2 eV-1 near the conduction band edge. The frequency dispersion in the accumulation region is attributed to border traps. A tunneling model was used to calculate border trap density Nbt.350 ℃ FGA is found to reduce the density of border traps from 7.1 ×1019 cm-3 eV-1 to 4.0×1019 cm-3 eV-1. These results demonstrate the FGA passivation is promising for the realization of high quality InGaAs-based logic devices.3. The Ge surfaces were cleaned and passivated by two kinds of chemical pretreatments:conventional combination of HF+(NH4)2S, and new one of HBr +-(NH4)2S. It is found that the combination of HBr and (NH4)2S can remove more Ge-0 bonds on the Ge surface compared to that of conventional HF and (NH4)2S with excellent stability. It is demonstrated that the capacitors with GeO2 passivation exhibit better electrical properties with less hysteresis, improved interface quality, and reduced leakage current. Interfacial and electrical properties of thin Al2O3 barrier layers combined with HfO2 caps gate stacks on S-passivated Ge substrates have been investigated. Results showed that Al2O3 barrier layer effectively suppresses the defective Ge oxide formation and improves the interface quality in terms of low Dit (2.83×1012 eV-1 cm-2) and decreased hysteresis. The annealed HfO2/Al2O3 gate stacks on S-passivated Ge have exhibited an equivalent oxide thickness of 0.94 nm and a leakage current of 1.22×10-3 A/cm2 at+1 V gate bias. A simple and effective process of improving Al2O3/Ge interfaces with low Dit has been demonstrated by using O2 oxidation. A low Dit of 4.9×1011 eV-1cm-2 is obtained after the 500 ℃ O2 treatments, which makes it a promising option for future Ge CMOS development. The insertion of an ultrathin La2O3 interfacial passivation layer effectively prevents the Ge outdiffusion and improves interfacial and electrical properties. A capacitance equivalent thickness of 1.35 nm and a leakage current density JA of 8.3×10-4 A/cm2 at Vg= 1 V are achieved for the HfO2/La2O3 gate stacks on Ge substrates. The valance band alignment and O 1s energy loss of (TiO2)x(Al2O3)1-x/Ge were investigated by x-ray photoemission spectroscopy. The results indicate that ALD (TiO2)x(Al2O3)1-x nanolaminates structures could effectively tune the interface quality and band offset of gate dielectric films on n-Ge.