The FPGA Implementation Of Rateless Spinal Codes

With the rapid development of wireless communication technology, efficient and reliable data transmission technology has received more and more attentions. In face of the increasingly complicated communication environment, it is difficult to obtain accurate channel state information in many cases. In order to adapt to this communication environment, rateless codes arise at the historic moment. The rateless codes have the characteristic of adaptive channel environment.Spinal code is a rateless code which can be adapted to the wireless network environment and choose appropriate rate to transmit signals according to channel state. It has proved that spinal codes can reach a rate approaching the Shannon limit in BSC and AWGN. The spinal codes have a simple construction, own a low complexity and can be implemented easily. The core of spinal codes is the pseudo-random hash function. The encoder divides the input messages into a number of blocks, then the child blocks will be transformed to transfer symbols continuously after the process of the hash function and the constellation mapping function. The decoder would accept transfer sequences constantly until decoding success or achieve the maximum transmission. In this thesis the decoding algorithm is bubble decoding algorithm, which essentially is a maximum likelihood(ML) decoding algorithm and to reduce the decoding complexity by cutting the poorer nodes in the decoding tree.In this thesis, the contributions are the FPGA implementations of encoding algorithm and decoding algorithm respectively, this thesis promotes spinal codes to the hardware level. The FPGA design for the decoder of spinal codes mainly includes three links, which are path expansion, path selection and traceback. And in every link, several design skills are adapted in order to improve the system throughput and reduce the design space. At the path selection stage, the simple and efficient bitonic sort algorithm is used to delete the nodes. And the local parallel processing strategy and pipeline technology all improve the system throughput greatly. The FPGA implementation results show that the spinal codes not only can achieve a rate approaching the Shannon limit on BSC and AWGN channel, but also can get a higher system throughput in his FPGA implementation. On the hardware, the FPGA implementation of encoder is realized, its throughput is 2.57 Gbps. And the throughputs of decoder are respectively 12.62 Mbps and 14.01 Mbps on BSC and AWGN channel. The FPGA implementation of spinal codes proves that the spinal codes not only has good performance, but also has stronger practicability.