A Study And Design Of Variable Gain Amplifier For Navigation Receiver Applications

With great development of “BDS-II” satelite system, the domestic market demand for terminal RF chip applied Beidou navigation is more and more intense, so high-performance receiver has become today's hot topic. Since the power of the RF signal received by the receiver have a large dynamic range, it needs the Automatic Gain Control(AGC) circuit to adjust the gain of the receiver chain according to the power of the received signal, to ensure the output signal be a constant power signal. Then the constant power output signal can be supplied to the post-stage circuit for processing, so that the AGC circuit is an essential module of a RF receiver. As a core module of AGC circuit, VGA's performance will directly affect the input dynamic range and the loop settling time of the AGC loop. With the continuous development of communication technology and CMOS process, the requirements for VGA's performance are getting higher and higher, so it's of great significance to study and design VGA.This thesis presents a variable gain amplifier applied to the “BDS-II” receiver, the VGA circuit applies the digital VGA structure, and specific circuit consist of two parts: the coarse gain-setting stage and the fine gain-setting stage. The coarse gain-setting stage includes four fixed gain amplifier(FGA), and all the FGA is settled with fixed gain of 14 d B. The four FGAs are cascaded through AC coupling mode, and four digital control signal S[3: 0] control switch on or off, by this, the coarse gain-setting stage achieve a gain range of 0d B~56d B with 14 d B coarse gain step. The fine gain-setting stage adopts a closed-loop feedback VGA structure, and it achieve 0d B ~ 14 d B gain range with 2d B gain step which is controlled by three digital signal T[2: 0]. Therefore, the proposed VGA ultimately realize a variable gain range of 0~70d B with 2d B gain step.The VGA was implemented in TSMC0.18?m RF CMOS process. The simulation results show: the VGA's gain range is 0.07 d B~68.4d B and gain error is less than 0.5d B, which shows the VGA have a high dynamic range and a good d B linear relationship; the VGA's IIP3 are-27 d Bm at 70 d B and 34 d Bm at 0d B; the VGA's noise figure are 39.5d B at 70 d B and 59.1d B at 0d B; when the frequency is 4MHz, the THD are 0.137% @ 0d B and 0.168% @ 70 d B, and the maximum power dissipation of VGA circuit was about 3.11 m A.The above results meet the performance requirements of BDS-II receiver.