| Digital radar system, for its high precision, high anti-interference ability and high stability, has become the direction in the development of new-generation radar system, and it has been widely used in military and civilian fields recently. Based on the implementation of FPGA and DSP, traditional radar signal processor usually with high cost could not meet the requirements of Missile-Borne Radar which is expected to have smaller size and lower power. With the continuous development and progress of IC, the processing ability of single chip has been significantly improved. With the advantages of high speed, small size, low power and high stability, the processor with the ASIC implementation is in large scale production at a pretty low cost. Thus, great importance should be attached to the design of radar signal processor with the ASIC implementation.Based on the theories of radar signal processing, this paper aims to conduct detailed analysis of the design of pulse doppler(PD) radar signal processor and the implementation of ASIC technique.The second chapter of this paper gives a general overview of the procedure of radar signal processing, and lays a foundation of the algorithm for digital down converter(DDC), pulse compression(PC) and moving target detection(MTD). As for chapter three, it gives introduction of advantages and disadvantages of IP-core-based processor with pipeline architecture. Although the design of radar signal processor based on IP-cores can shorten the time needed for a design cycle and pipeline architecture has large data throughout.The PD radar is in an intermittent work pace,there are three time period for the PD radar, including the signal transmitting period, signal receiving period and switching coherent processing period(CPI). In each time period, there is only one of the three IP cores in working condition.Therefore, this kind of architecture has a disadvantage of low utilization in hardware resource. In order to improve the utilization in hardware resource, the thesis puts forward a time-division multiplexing processor structure. Combined with the characteristics of each process operation, this paper give an analysis of the operations and hardware resources required in each time period according to the configurable length of the pulse compression from 64 to 1024 point and the configurable pulse number of MTD from 8 to 64.At the meantime, the thesis fulfills the task of the design and implementation of the processor.Finally, the functional verification,implementation and formal verification are done for the processor.A verification platform is built with Matlab and Modelsim in this paoer,and is used to verify the function of PD radar signal processor. For different configuration, the thesis makes a comparision between the results of the PD radar signal processor and the results of Matlab model. In addition, it gives an illustration of the relative error of the two computing results via caculation. The value of relative error is about 10-4, which means that the precision meets the requirement of radar signal processing,consequently, the function of the circuit is correct.Then, by using Design Compiler of Synopsys, the implemenation of the proposed design is completed in 0.1 version of SMIC 0.13?m technology library of Veri Silicon.As the results of the report, the frequency of design is 200 MHz, and the processor can complete signal processing timely at this frequency. And the size is about 8858093.855 ?m2,the area of PC IP core and MTD IP core are saved, and the whole processor area decreased by 17%.At last, the formal verification with the Formality is performed to ensure that the gate-level netlist is equal to the RTL design. |
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