Hardware Accelerated Design Of Radar Sparse Signal Processing Algorithms

As an emerging signal processing technology, sparse signal processing provides a framework of reconstructing the original signal with a small amount of data. Compressive sensing(CS) is a new sparse signal processing theory, which has experienced great development in various areas since it was proposed. Especially in the researches on extracting target information with the incomplete radar echo data, CS reflects its great application value. Compressed sensing is mainly composed of three parts, which are the sparse representation of signal, the selection of measurement matrix and the signal reconstruction algorithm. The application of signal reconstruction algorithm in radar signal processing and its accelerated hardware implementation are the focuses of this thesis. Considering the huge computation of the sparse reconstruction algorithm, in order to meet the real-time requirements of radar signal processing, we adopt field programmable gate array(FPGA) which has richer resources and stronger parallel processing ability to implement the hardware acceleration of the reconstruction algorithm.In this paper, we mainly study the method of target detection based on sparse signal processing in frequency-agility radar(FAR) and sparse stepped-frequency radar(SFR). Orthogonal matching pursuit(OMP) algorithm is utilized to implement the valid information extraction and target signal reconstruction due to its high reconstruction accuracy. Finally, accelerated FPGA implementation of the reconstruction algorithm is realized. The main works of this dissertation are as follows:Firstly, we introduce the content and principle of sparse signal processing. Then the advantages and disadvantages of different signal reconstruction algorithms are discussed, with emphasis on greedy algorithm and gradient pursuit(GP) algorithm. Moreover, we briefly describe the application of sparse reconstruction technology in radar signal processing.Secondly, theoretical analysis and feasibility verification of the application of CS technology in the target detection of FAR are carried out. First, the operational principle of FAR is briefly introduced. Then a scheme based on sparse reconstruction technology is proposed to solve the long coherent accumulation time and complex signal processing in the traditional FAR, and OMP algorithm is utilized to achieve the signal reconstruction. Considering the huge computation and time consumption of OMP algorithm, this thesis optimizes OMP in two aspects. One is reducing the iteration times of least square(LS) part by the orthogonal processing of support set. The other is using Conjugate Gradient(CG) method instead of matrix decomposition to solve the LS problem, which has lower computational complexity and faster convergence speed. By these two optimizations, a low-complexity algorithm called OMP-CG algorithm is obtained. In addition, the effectiveness of OMP-CG algorithm on stationary and moving target detection in frequency-agility radar is verified based on a set of measured data. Finally, the accelerated FPGA design of OMP-CG algorithm is implemented based on XC7VX690T FPGA platform.Thirdly, the feasibility of sparse signal processing to reconstruct the high resolution range profile(HRRP) in sparse stepped-frequency radar is analyzed theoretically and verified by measured data. First, we introduce the operational principle of stepped-frequency radar, compare the characteristics of the traditional stepped-frequency signal and the sparse stepped-frequency signal, and obtain the sparse representation of stepped-frequency radar echo signal. And then, based on the characteristics of stepped-frequency signal, a further improvement of OMP-CG algorithm is proposed. According to the prior extraction information of observation matrix, zero-padding to residual vector is conducted so as to carry out IFFT that is capable of calculating the correlation between residual and dictionary, simplifying the construction of the sparse matrix and reducing the computation complexity of the correlation part from O(N~2)to O(Nlog N) as well. The optimized algorithm is called SFOMP algorithm. Finally, a set of measured SFR echo data are utilized to verify the HRRP reconstruction performance of proposed SFOMP algorithm and its hardware acceleration is implemented based on XC7VX690T FPGA.