The Algorithm Research And Circuit Design On Digital Controlled AGC For GNSS Receiver

In recent years,the satellite navigation system has a wide application field.At the same time,users’ demands for receiver have increased.The factors,especially the interfering noise and the inner circumstance have effects on the input signal amplitude when receiving satellite signal,what will cause the inaccuracy.Therefore,the AGC loop becomes a very important part to control the signal automatically.The Automatic Gain Control(AGC) loop in the GNSS receiver RF front-end chip is mainly discussed in this paper.The designed loop is digital-controlled,closed-loop structure,and it is composed of ADC,PGA and AGC.The received signal power is lower than the thermal noise,therefor it is actually dominated by thermal noise with Gaussian distribution.Based on the Lloyd-Max algorithm,the 4-bit non-uniform quantization ADC Model is designed.Compared with the 4-bit uniform quantization ADC,the model improves the SNR by 3 d B in the small-signal region.So the adjusting accuracy of the AGC loop which set small-signal region as amplitude estimate region will be improved effectively.The conventional digital controlled AGC loop has some drawbacks,such as the low speed and instability.In terms of these,the paper introduces a fast adjusting algorithm based on the amplitude value statistic.The Gain adjusting procedure is optimized to at most two steps,which raises the adjusting speed.In addition,the signal mutation during and after adjustment can be dealt with well.The proposed design can significantly reduce the circuit size and improve the loop stability.when circuit works in 62 MHz clock,the algorithm shortens the adjusting time to 16μs to 32μs.The algorithm based on amplitude statistic works well with the multi-bit ADC.However,it can not be used accurately when work with the 2-bit ADC.Because the signal amplitude value quantized by 2bit-ADC isn’t enough accurate.Considering the defects,a fast adjusting algorithm based on the proportion statistic is put forward.This algorithm has the same advantages as the algorithm based on amplitude statistic,except for one more adjusting step.More importantly,this algorithm can work with multi-bit ADC and 2-bit ADC,without compensating the clipping error.when circuit works in 62 MHz clock,the algorithm needs32μs to 48μs to adjust.Besides,the dynamic gain range of the PGA is within the boundary(-10 d B,52 d B),the step is2 d B,and this will meet the adjustment range that AGC needs.The AGC loop circuit is applied in GNSS receiver RF front-end chip and implemented in0.18μm CMOS process.The loop is composed of the PGA,4-bit uniform quantization ADC and the AGC algorithm based on the amplitude value statistic.The PGA and AGC algorithm circuit totally occupy an area of 0.21mm2.The measurement result achieves the designing goals.