| Currently,the transmission bandwidth of backbone network in optical fiber communications growth with a rate which is more than 50% per year, and the cost of 100 Gbps and 40 Gbps optical module device is much smaller than 40 Gbps and 10 Gbps optical module device. Therefore, more and more people requires a backbone transmission network which can support 100 Gbps transmission, this make a point 100 Gbps is a development direction. DSP chip is the most important part of 100 Gbps DSP chip, there are more than 70 million logic gates in the first generation of hard decision ability of the 100 Gbps chip, while the latest 100 Gbps DSP chip with soft decision ability has more than 130 million gate circuits, which using differential mode in long optical fiber transmission, and each path can handle 32 Gbps rate data. How to make such a difficulty chip, it’s depends on whether its performance, stability and robustness can achieve the anticipation results. The key point is design a system which should be combine the actual situation and can be used for test verification platform for the chip.Since the chip requires huge logic resources, large data and high clock frequency, if we use FPGA to make a system-level verification without any changes, the material cost and labor cost will be expensive. Also, because of the difference of ASIC and FPGA logic design, and the limitation of single FPGA resources and high-speed interface, ASIC chip needs to be design to a certain type which should cut FPGA to multi-chip and implement it in parallel mode, which will increase the difficulty of development and maintenance, will increase the difficulty of verification too. This thesis is accord to a real system and imitate a real environment by reducing the symbol rate which does not change the chip algorithm, then build a verification platform on FPGA in thus environment. This system is made of two parts: hardware veneer and logic with adjustable and measurable. The date of the verification system come from a real channel, which has the function to regulate different modes. During the verification, the test starts from a real application scenarios, and the testing is well planned, the verification platform is built with high adjustable and measurable. When relate to the self-check of the system, it’s using the business data come from a real channel. The greatest advantage of the verification platform is that can highly support the real business data verify in different environment and multiple model, it also can support the adjustable and measurable of the key node in a alone subsystem, which can improve testing efficiency and locate the problem accurately. the digital domain inner loop function is included, which can guarantee the accuracy of the verification platform, then it can get a reliable result as far as possible.The main purpose of this platform is to verify 100 DSP chip algorithm is right or not, if we find bug, we can use this platform to capture related data and analysis them, and it also can locate the problem timely and effectively. We used this platform verified the performance, stability and robustness of the 100 Gbps DSP part by part. We also compared the results with the results from an ideal algorithm simulation platform, which required the performance differential losses in 0.5db, and check if the each index with exception or not after a long run to verify the stability. To verify the robustness, we simulate various abnormal situation artificially, then check if the whole system can completely back to normal within the specified time or not after the periodic line recovered. According to the actual environment, planning a validation use cases. The results obtained from the authentication platform show in terms of performance, the DSP algorithms than would like authenticity can manage poor performance + 0.3db. Stability under simulated worst of little real channel operating environment for 24 hours, BER statistics without exception, each reported to register no exception. Robustness in terms of man-made various kinds of exceptions, the environment after the return to normal, the system can return to normal in less than 50 ms. The results showed that all of the indicators of the chip are expected to meet the needs of the algorithm. |
