Study On Parallel Decoders Of LDPC Codes And CUDA-based Implementation

Low-Density Parity-Check(LDPC)codes was firstly proposed by Gallager in 1962.With the improvement of the computer simulation and the renaissance of modern coding theory,LDPC code has aroused extensive attention among the Channel coding theory researchers. As a kind of good codes with near-Shannon limit performance, LDPC codes are not only simple in design, but also have a larger advantage in the error correction ability, the decoding performance and the hardware implementation complexity.Therefore,LDPC codes have a broad prospect of application in many communication systems.In recent years, the implementation of efficient encoder and decoder for the LDPC codes has become a popular spot of research gradually,and there is an increasing demand for high-speed data rates.In general,the design of encoder and decoder for LDPC codes can be implemented by different computing platforms, such as CPU,GPU and FPGA. Recently, using the parallel computing ability of GPU to accomplish algorithm acceleration is becoming more and more popular. To solve the delay problems of the decoding based on the CPU platform,the thesis proposes a decoding scheme of LDPC code based on CUDA.CUDA is a kind of parallel architecture,which can provide enough support for GPU general computing. The thesis studies the hardware system and software system of CUDA architecture in the beginning, then introduces the basic principle of LDPC codes and mainly introduces the scaled MSA algorithm. Combining these two parts with the hardware and software environment,we implement the specific encoding and decoding scheme based on the CUDA,and finally we analyze the factors influencing the decoding rates of the system. Comparing with the simulation performance of LDPC code decoding based on the CPU platform, the thesis proves the fact that using CUDA parallel decoding can guarantee the decoding performance, and achieve the acceleration of decoding rate at the same time.The scheme effectively reduce the decoding delay and improve the system throughput.