A Design And Implementation Of High-speed I/O Protocol Data Link Layer

With the advent of the era of big data, bandwidth and speed of the bus have gradually became the critical factors that restricted the development of the computer system. The PCI Express, which serves as the third generation high-speed serial bus, has overcame the interference between parallel data lines and synchronization issues. In addition, it introduces a number of new features, for example, it is able to support the multiple data routing based on multi-channel data transfer mode, to take fully into account the Qo S(Quality of Service) issues based on packet-based data transfer mode. As a high flexibility, high stability and reliability, affordable cost and scalable general-purpose I/O protocol, PCI Express has been recognized as the next ten on the bus standard. However, due to the technical difficulties of PCI Express, along with the blockade attitude from foreign counties, most of the PCI Express domestic companies prefer to purchase the commercial IP directly. The idea of PCle utilize the concept of the stratification, which starts from the top to bottom with the transaction layer, data link layer and physical layer. The physical layer is also divided into logical sub layer and electrical sub layer. With the cooperation of each layers, it achieves the high speed transmission of PCI Express link. As the thing layer and the intermediate layer of physical layer, the data link layer has served as the important safeguard of the reliable data transmission. The data link layer is not only responsible for the packaged data transfer and exchange work, but also responsible for the generation of CRC and TLP error detection and retransmission of data and work flow control work. It also has the ability to use the ACK/NAK protocol to ensure reliable delivery of packets. Without security work data link layer, the PCI Express agreement will cease to exist.The paper presents a design method of high-speed I/O data link layer of the protocol st ACK. This is used for the data center and is based in the high-speed I/O protocol stack PCI Express3.0 built. Firstly, this paper did the research about the background and development status of PCI Express research. In order for readers to gain a deeper understanding, this paper focus on the data link layer and described in detail the function and hierarchy of PCI Express protocol. Furthermore, it presents the design of high-speed I/O protocol stack data link layer, including the interface signals, design diagram, state transition diagrams. Finally, it utilize the platform that system Verilog built to verify the system design simulation. Through the analysis of the overall results of ISE tool and waveform that caught by the FPGA validation logic analyzer(chipscope), we here certify that it achieves the design and implementation of the basic functions of the data link layer.