The Design And Application Of Leading Zero Anticipation

All along, the capability of the floating point operation is essential for the assessment of microprocessor performance. With the development of microelectronics technology, high-performance Multiply-Add-Fused and adder have a high status in the design of floating-point unit. Leading Zero Anticipation is parallel with the adder, which calculates the leading one position of the floating-point addition result. And the number of leading zeros is detected by Leading Zeros Detector. The normalized stage of IEEE-754 standards is optimized by Leading Zero Anticipation. It is a key part of the high-performance Multiply-Add-Fused and the adder.There are two leading zeros anticipation according to the prediction accuracy, one is the accurate prediction, the other is one-bit error prediction. In the thesis, two different accurate predictor structures and three-operand Leading Zero Anticipation are implemented by the algorithm of Leading Zero Anticipation.As shown below, the main work of this paper contains:Initially, in this thesis, the basic algorithms and the classic structure of Leading Zero Anticipation are introduced, the implementation and application of Leading Zero Anticipation are described in the conventional structure of Multiply-Add-Fused.Secondly, the two main algorithms of the accurate prediction are discussed, including Leading Zero Anticipation with concurrent position correction and Leading Zero Anticipation based on carry signal correction. The encoded sequence patterns are detected by the algorithm of concurrent position correction, and the error correction signal is attained ultimately. The carry signal in adder is used by the algorithm of based on carry position correction, and determine whether the prediction error arises. Meanwhile, the algorithm of three-operand Leading Zero Anticipation is described.Then, Leading Zeros Detector is designed in the thesis. Leading Zero Anticipation with concurrent position correction and Leading Zero Anticipation based on carry signal correction are implemented in the thesis. The entire concurrent correction circuit is performed in parallel with the adder, which could reduce the circuit delay and improve the circuit performance. As for Leading Zero Anticipation structure based on carry correction,the use of carry signal in adder makes the circuit logic more simple and circuit area smaller. Three-operand Leading Zero Anticipation is implemented by the algorithm.Finally, the thesis compares the three structures and analyses their own features and application condition. And the circuit description of the three structures are completed by VHDL hardware description language. The functional simulation of the circuit is completed to ensure the correctness of its functions. Logic synthesis is implemented at the same time, which could test the circuit performance.