FPGA Architecture Development Based On Neural Network

There is increasing interest in developing Field Programmable Gate Arrays(FPGA) architectures with new logic blocks containing specific functionality, such as digital signal processors and memory blocks. In the development of new FPGA architectures, a key part is to evaluate different logic block architectures and routing architectures in the early development stages and determine their impact on the demand for routing wires. This demand was conventionally determined through experimentations, which usually needed enormous time and efforts. This gives rise to the need for routing channel width model and average wirelength model that could be used to evaluate different architectures at the early development stages.This thesis proposes a neural network(NN) and a knowledge-based neural network(KBNN) modeling approaches for FPGA architecture development. First, we leverage neural networks to derive accurate models of the routing channel width in homogeneous FPGA architecture. The resultant models can be used in the early stages of FPGA architecture development to facilitate fast design space exploration. Then, we propose a KBNN modeling approach for homogeneous FPGA logical architecture design. The KBNN embeds the existing FPGA analytical models into a neural network. The neural network can complement the analytical model accuracy, while maintaining the meaningful trends successfully captured in the analytical models. The obtained KBNN predicts the routing channel width by circuit implementations on various FPGA architectures. Finally, we leverage KBNN to explore heterogeneous FPGA architecture design. Given a set of circuits, the design objective is to find an FPGA architecture which achieves the minimal wirelength and well matches. The approach can guide the trade-offs between the architecture parameters in early-stage architecture development.Neural network models show significant improvement over existing estimation approaches, and our models have been applied to FPGA architecture development scenarios to demonstrate its practical application and effectiveness.