Study On Delay Estimation Method Of FPGA Circuits Based On Knowledge-based Neural Network

Field programmable gate arrays?FPGAs?are adopted in many electronic systems,due to their design flexibility and high performance.For providing right FPGAs for different applications,FPGA architectural exploration is needed.When developing a new chip,the accurate delay,area,and power are obtained to evaluate the architecture.In these metrics,the delay is particularly critical.However,the approach based on the experiments is very time-consuming,and the analytical model based method is not accurate enough.In this thesis,a knowledge-based neural network?KBNN?modeling approach is proposed to estimate the FPGA delay in high accuracy and high speed.The proposed the model based on KBNN which is the combination of Elmore delay model and MLP?Multilayer Perceptron?neural network.The physically meaningful and the relationship between the parameters is represented in the model which can offset the error of analytical model.The model with high accuracy and high speed is comprehensively considered the parameters which have impacts on the delay.The obtained delay model takes the transistors size as inputs,and can be applied to the transistor sizing process to optimize the delay and area simultaneously.The established delay model also can be integrated into the existing FPGA architecture exploration tool to shorten the design cycle.In addition,the delay is not only affected by architectural parameters,the variations of transistor-level parameters,V_dd and V_t,which can reduce power consumption,also have great influences on circuit delay under the development trend of low-power design and deep sub-micron technology.As a result,the FPGA delay model considering V_dd and V_t is necessary to be built with KBNN,which in favor of exploring the relationship between delay and power.The proposed model can discuss the variability of architectural level and transistor level parameters during the FPGA architectural exploration process,and avoid the complex process of generating the transistor model for different V_dd and V_t in the experiment,leading to a more direct relationship between input and output with high flexibility.