The Hardware Modeling And Reconstructable Implementation Of The Forward Channel Of The Spiking Neural Network

Spiking neural network is regarded as the third generation of neural networks, and it has attracted many researchers. Its advantages have been shown in pattern recognition and computer vision. The implementation of the spiking neural network in the hardware is an important method to show its powerful computation ability. At present, there are a few classical mathematical models describing the SNN, which lead to excessive consumption of hardware resources and time resources. Therefore, based on the spike response model, a model suiting to the implantation in the hardware is built in this paper. The new model approximates accurately the spike response model and cuts down the consumption of the both resources. According to the synapse model, the synapse circuit is designed in the Simulink platform and the simulation result is achieved. Then, based on the synapse circuit, a whole forward channel of SNN is generated, which is tested using the XOR problem. Afterwards, the forward channel is implemented with reconstructable FPGA. Finally, the conclusion and the future work are discussed.