Design And FPGA Implementation Of Baseband Unit For DS/FH Communication System

Because of the strong anti-jamming and anti-interception capability of the spread spectrum technology,it is widely used in military communication field.In spread spectrum technology,the DS/FH hybrid spread spectrum technology,which combines the advantages of direct sequence spread spectrum and frequency hopping technology,can break through the bottleneck of a single spread spectrum technology,so its ability to resist interference is more powerful than a single spread spectrum.At present,the technology of hybrid spread spectrum communication has become a hot spot in the research of anti jamming technology.This paper is based on the "xxxx system" of laboratory research project,the purpose of this project is to develop a hybrid spread spectrum communication system,which can transmit and receive the short data in a very low SNR condition.In this paper,the design of the synthetical baseband unit for hybrid spread spectrum communication system is studied,and the design scheme of the integrated baseband system is given.The simulation of the integrated baseband system is carried out by using MATLAB software,simulation results show that the system can be used in the condition of very low SNR.On the basis of theoretical analysis and simulation,the design of the integrated baseband unit is realized based on FPGA,and the detailed implementation of the key modules is given.In the process of the baseband unit design,the following problems are studied in this paper:1.According to the requirements for the system parameters,the protocol frame structure of the system is designed.The protocol frame consists of a leading sequence,data frame,service timing sequence,the preamble sequence and service timing sequence were undertaken for system synchronization and maintain synchronization function.2.Due to the presence of frequency hopping,the Doppler shift of different frequency hopping slots is different.If the traditional symbol level modulation method is used to modulate the data,then it is not possible to transmit the data from the same symbol in a frequency hopping slot,so that the same symbol data can be used to carry out different Doppler shift.In order to solve this problem,this paper uses a chip level modulation method,the modulation method proposed in this paper can reduce the effect of the Doppler shift on the system.3.In order to guarantee the synchronization of the system in the condition of very low SNR,a synchronization scheme suitable for this system is designed,which combined DS synchronization with FH synchronization for discussing closely.The simulation results show that the propose scheme can achieve the synchronization of the system under the condition of very low SNR.4.Since the data of the paper is to be transmitted after tail biting encoding,so the receiver can only get the correct data after the corresponding decoding.Aiming at the shortcomings of high complexity and not fixed delay of decoding algorithm for Tailbiting convolutional codes,a new algorithm based on SOVA is proposed,which reduces the complexity of decoding and has a fixed decoding delay.Simulation results show that the BER performance of the algorithm proposed is close to the maximn-likelihood algorithm and better than the circular Viterbi algorithm.In the implementation of the baseband unit based on the FPGA,the paper optimizes the FPGA implementation of the following modules:1.FPGA implementation of baseband shaping filter module.In this paper,the full parallel structure of DA algorithm is used to realize the FPGA implementation of shaping filter.In the FPGA implementation,the storage structure of the algorithm is optimized,which greatly reduces the use of FPGA memory storage resources.2.FPGA implementation of signal detection and synchronization module.This module needs to consume a large number of FPGA storage and logical resources,in order to achieve the success of the module in the FPGA,the structure of the multiply accumulator in the module were optimized.Since the use of storage resources is a fixed value,it can only improve the use of storage resources of FPGA.In order to achieve this purpose,the use of storage resources of FPGA are detailed planning.After planning,various types of storage resources in FPGA have been fully utilized.3.The FPGA implementation of the decoding module of tail biting convolutional code.In order to facilitate the implementation of the decoding algorithm proposed,we divide the algorithm into Viterbi decoding module,soft information calculation and update module,initial state selection module,decoding information buffer and adjustment module.The functions of these 4 modules are introduced in this paper,and the FPGA implementation of the four sub modules and the simulation results are given.