Font Size: a A A

Thermo-mechanical Reliability Analysis Of 3D Stacked Package With Through Silicon Via

Posted on:2016-09-15Degree:MasterType:Thesis
Country:ChinaCandidate:D Y WangFull Text:PDF
GTID:2348330479954471Subject:Mechanical engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of microelectronics industry, the requirements for packaging electronic products become more and more high, which makes the key technologies in package industry be improved. The emergence of TSV(Through Silicon Via)brings the whole package industry into a new turning point. As a new technology, TSV exists many problems due to the ultra fine-pitch. Considering the fatigue and failure in the package,thermo-mechanical reliability analysis for the key part of 3D stacked package becomes the key development of this technology. To avoid the failure caused by thermal deformation in key part of package structure under the thermal load, This paper research the following several aspects.Firstly, the thermal mechanical response of a single TSV under thermal load and the material parameters used in electroplated copper are studied. After times of finite element analysis, the difference between the size and distribution of stress, and the mechanism of size and distribution of stress is summarized. In addition, the influence of structure parameters is explored.The analysis results of a single TSV with the same structure parameters using 2D model and 3D model are compared. After several modeling analysis, we draw the similarities and differences in the stress size and distribution by two models.Secondly, the application scope of 2D top view and axial view are studied by analytical method and simulation method together. Through the study, we conclude that the simplified2 D axial model used in 3D-Packaging can accurately reflect the mutual effect among stacking chips.Finally, simplified 2D axial model of multi-stacking chips is established, and its overall deformation and stress distribution and size of the key part are researched. Besides, the effect figures of structural parameters including TSV diameter, micro solder height, TSV diameter in intermediary layer, intermediary layer thickness and normal solder height are demonstrated.This paper provide scientific basis for the TSV design and have far social significance to the development of electronic packaging industry.
Keywords/Search Tags:Through Silicon Via, Thermo-Mechanical Reliability, 3D Package, Electroplated Copper, Multi-Chip Stacking
PDF Full Text Request
Related items