Research And FPGA Implementation Of PAPR Reduction Technique In Wideband-OFDM System

Orthogonal frequency division multiplexing(OFDM) is a high-speed transmission technology in wireless environment, which takes advantage of the orthogonality between subcarriers to improve data transmission rate, not only can effectively combat multi-path fading and Doppler frequency shift, but also can greatly improve the spectrum utilization. But it s inherent disadvantage is the high peak to average power ratio, which is higher, if the bandwidth is wider. When the transmitted data with high peaks are passing through nonlinear devices or channels, the signal may suffer from significant in-band distortion and spectral spreading. Therefore, in the practical application we should back-off the power of the power amplifier, which would reduce the efficiency of the power amplifier.The PAPR reduction techniques can effectively reduce the amplitude of the peak signal, and it is one of the effective ways to improve the efficiency of the power amplifier. In the paper, we focus on the analysis, design and FPGA implementation of the peak cancellation crest factor reduction algorithm. Firstly, proceeding from the basic principle of OFDM system, the reason for the existence of high peak to average power ratio and its effect on the performance of the communication system are presented. Then the operational principle of the PC-CFR algorithm is described and is designed as a m-file in MATLAB to analyzes the effect of the crest factor reduction under different parameters, so that we can make sure the peak detection algorithm, the parameters of the prototype filter and the number of iterations that would be used in the FPGA logic design. And the unfixed delay from the peak to peak indicator is solved. Finally, based on the idea of “Top-Down” hardware design, the paper divides the PC-CFR algorithm modules according to different function and defines the interface signal for each other. Then the hardware logic design and RTL simulation of each module is completed in the software of System Generator, and is debugged and verified in the Xilinx's ML605 evaluation board. All of that indicate the logic design correctly.A LTE signal, which bandwidth is 20 MHz with QAM16 modulation, is used for function simulation and FPGA hardware testing. When the EVM is less than 7%, the PAPR of signal can be reduced by about 3.39 d B, and the dynamic power consumption of the whole hardware design is about 275 m W. It can improve the efficiency of the transmitter so effectively that can make the energy consumption low and cut down the operation cost. So it is worthy to be carried out in the practical application.