Ofdm System Papr Suppression Techniques

Orthogonal Frequency Division Multiplexing(OFDM) is a parallel transmission technique of multi-carrier modulation, the principle of which is to convert a serial high-rate data stream onto multiple parallel low-rate orthogonal sub-carriers. Compared with the traditional single-carrier system, OFDM dramatically improves the spectrum efficiency, minimizes the effect of frequency-selective fading and reduces the complexity of the equalizer. However, as the OFDM signals are the sum of signals with random amplitude and phase, they are likely to have large peak-to-average power ratio(PAPR) that requires a linear high-power-amplifier with an extremely high dynamic range, which is expensive and inefficient. High PAPR is one of the major drawbacks of OFDM, so this paper put great emphasis on the research of PAPR reduction.At present, the most popular three kinds of PAPR reduction techniques are pre-distorting algorithm, scrambling algorithm and coding algorithm, all of which have been introduced and analyzed in detail in this paper. Through the comparation of performance of the algorithm mentioned above, this paper improves the repeated clipping-and-filtering (RCF) algorithm proposed by Jean Armstrong, putting forward a new method of utilizing Hanning window to filter the out-of-band noise in the frequency-domain, which is called CF-HW algorithm for short in this paper. The simulation results show that, this method dramatically reduces the PAPR as well as provides lower bit error rate(BER) and computational complexity. Though it introduces some out-of-band components, it can still limit the out-of-band power to meet the requirement of transmit spectrum mask specified in the IEEE802.11a and HIPERLAN/2 standard.Moreover, this paper accomplishes the FPGA implementation of PAPR reduction based CF-HW algorithm. First, divide this project into several modules and design each module in proper way, in particular, improving the traditional implementation method of clipping. Then, execute the joint debugging and timing simulation in the development environment of QUARTUS II 8.0. At last, complete the design of the hardware circuit based on the FPGA of EP3C40Q240C8N produced by Altera and the quadrature digital upconverter AD9857 produced by AD, realize the PAPR reduction operation on the hardware platform, and verify the correctness of the CF-HW algorithm through the test process.