Design And Implementation Of Placement Module In FPGA Software Development System

Although domestic FPGA hardware technology continues to develop andprogress,but FPGA designs totally rely on FPGA software development platforms.This will not only seriously hinder the rapid development of the domestic FPGAtechnology, and can not be guaranteed in security. If you do not use the softwaredevelopment platform for FPGA designs,although it can be partially strengthened insecurity, but it requires the users to have very much knowledge of FPGA and tooinefficient. Domestic FPGA market requires that the FPGA providers can providenot only FPGA products, but also FPGA software development system.This paper analyzes the current situation of FPGA technology, FPGA softwaredevelopment platforms and placement algorithms. Combined with the currentsituation and actual needs, the placement module has been fully bussiness?functional and non-functional requirements analys is.According to requirements, thedifficulties are to establish the system device model, data model, scalable design,placement optimizationthe. Use the key technologies to solve difficulties.Requirements and technical analysis is the solid foundation of design andrealization.Then,this paper describes the design and implementation of the placementmodule. Use C++and TCL to realize the module. Use XML to model device andsave messages. The placement module is divided into four blocks: device model,data model, placer and timing analyzer.Use device module files to describe theFPGA physical information,including resouce type,quantity,location,etc.. Read XMLfiles into memory when using one model. Data model is ma inly stored netlistinformation. Placer perform real placement operation, matching instances of datamodel to spots of device model. Placer use simulated annealing algorithm tooptimize solutions and call timing analyzer to get cost for each placement soluton.Timing analyzer use static strategy and critical path algorithm to calculate cost.Finally, through unit testing and integration testing,it detect potential defects inthe placement module which we need to fix. By analyzing the test results shows theplacement module can work normal and meet requirements. But in performance,there is a big gap between placement module and ISE. In the future, placer andtiming analyzer need to be adjusted and optimized according to the actual usage.