RF Receiver Study For A 5.8GHz ETC SOC

The Electronic Toll Collection system,or ETC,is an important part of Internet of Vehicles.Its technology covers analog,digital,and mixed signal,and has high value academically and commercially.Based on the theory of design and measurement of RF integrated circuit,this thesis studied in details of the key front-end blocks in a RF receiver for a 5.8 GHz SOC.Circuit design principles have been explored.Simulation and measurement have been performed to verify the relevant performance.Through the investigation to the ETC history and current development status globally,and from the requirement of the communication system standard,this thesis proposed the circuit block design requirements for the 5.8 GHz RF receiver in an SOC using a top down methodology.The SMIC0.13 μm EEPROM CMOS technology has been used for the circuit design.At the circuit level,this thesis focused on the LNA and mixer used in the RF receiver designs.For the LNA,it started with the overall system design considerations,and then the specifics for LNA under various topologies.Based on the system requirements,a source de-generate based,single-end in,and deferential out structure has been proposed.The circuit gain can be controlled digitally.The noise figure,third order interrupt point,and stability have been simulated.Also at the circuit level,the principle,category,design target of mixers are investigated.A double balanced structure with a Gilbert Cell,resistive load,and common source-gate input has been used to design a digitally controlled mixer.The gain,noise figure,and the third order interrupt point have been simulated.Also discussed in this thesis is the layout factor in the RF circuit performance.Another important element in the RF IC is the measurement.The RFIC related measurement principle and application to the actual 5.8 GHz chips have been discussed.The results summarized the following: DC current of each circuit block,gain for each block and the total Rx chain,sensitivity under given BER,input matching,IF output interception,noise figure,DC current under sleep mode,RSSI,IF output Vs.input relationship and its temperature dependence,and some transmitter tests.Overall,this thesis discussed the simulation and measurement principle,methodology,and flow,in complete details from system to circuit,layout,and measurement,for a 5.8GHz ETC SOC.The measurement results show this chip can meet the requirement for such a5.8GHz ETC system.