A Design Of AFDX End System

With the development of avionics systems,the electronic systems within the aircraft are becoming increasingly complex,the transfer of the various flight data needs to be done in a shorter period of time.A high transmission speed,high reliability,strong deterministic data bus has become an important criterion forjudging whether the avionics systems are advanced or no.The prior common airborne data bus ARINC429,MIL-STD-1553 is no longer applicable to the current avionics system information transmission requirements,due to the accelerating process of avionics system integration,the data exchange and communication,the resource management and sharing among airborne equipment,which require the on-board data bus has a higher performance.AFDX network combines the advantages of standard Internet and continuous optimization,has gradually become the mainstream of the airborne data bus technology.AFDX network not only transfer data fast,a large-scale transmission,but also combines with the unique deterministic load configuration information technology and the introduction of virtual link,gaining a more deterministic,higher reliability characteristics,can be well adapted to the current requirements of the new avionics interconnected systems.In order to achieve a reliable information transmission among the avionics subsystems,this paper based on AFDX network end system protocol standards and the previous AFDX network bus technology research results,designs and achieves a programme of AFDX network end system based on FPGA.This paper firstly introduces the protocol standards and basic composition of AFDX network,introduces the concept of end system,and constructs a end system frame based on FPGA to implement the function of the end system;secondly,introduces the hardware of end system which uses FPGA as the core chip,combines with the peripheral circuit design and hardware device selection;then,this paper designs the software of system mainly from the aspects of data transmission and reception of end system protocol stack;considering the needs of different scheduling algorithm when end system processes data,this paper discusses a priority-based scheduling algorithm and classical scheduling algorithm is compared in terms of performance and builds a test platform in the laboratory,verifying the performance of send and receive frame of end system.The design uses a field programmable logic device FPGA chip as the core chip,notonly can reduce design time and experimentation cycle,but also save resources;while FPGA programming is flexible,and its IO resources are rich,can achieve more different purposes.The simulation results show that the end system accurately and reliably achieve the desired function,has a certain value and promotion prospects.