Implementation And Verification Of A Fibre Channel Protocol Processing Module

With the development of avionics system,Fibre Channel has been widely used in avionics systems,thanks to its high performance,high reliability and low cost.The FC-AE-ASM protocol,which belongs to the FC-AE protocol family,provides a stable,secure and low latency communication mode to support the real-time and bi-directional communication between two ports in avionics networks.With the increasing communication demand of avionics system,the original FPGA-based FC-AE-ASM protocol processing equipment can not satisfy the requirements of processing speed,size,power consumption,etc.So the protocol chip using So C technology emerges as required.This thesis is based on the FC-AE-ASM protocol chip research project.Based on the study of FC,FC-AE-ASM protocol and new generation avionics network architecture,this thesis is involved in designing ASM data receiving module and independently completing the verification task of this module.The main content is discussed as follows:1.The research on the basic definition of the FC protocol is done,such as hierarchical structure,data structure,network topology and so on.The application of FC-AE-ASM protocol in avionics system is disscussed in detail.Based on the hardware-software partitioning,three implementation methods of FC protocol engine are compared.The advantages of So C-based implementation method are discussed in five aspects of processing speed,power consumption,size,area and cost.2.The FC-AE-ASM protocol chip is described by architecture,on-chip resources,data organization and sub-module functions.In particular,the function of FC-AE-ASM protocol processing is analyzed from two aspects of data transmission and data reception.The module structure,function,data stream,interface signal and timing of ASM data receiving module are described.What' s more,this thesis details the data receiving memory cell management module and its sub-module,including the description of the key signal of the module,the buffer unit address assignment principle,buffer unit occupancy flag management mechanism,state machine and buffer unit scheduling method.3.On the basis of a study of the function verification and the hardware-software co-verification method,the verification of the ASM data receiving module is completed,which ensures the correctness of the function of the module.The concrete task contains the establishment of the verification platform,the design of the verification model,the planning and implementation of the verification and so on.Because verification model plays an important role in the development of verification,the focus of the work is on model design.For the verification of this module,the verification includes 72 and 88 verification items in the module level and system level,respectively.4.The delay analysis of ASM data reception is completed by using the system level virtual verification platform.The receiving delay of the long message and the short message is analyzed and calculated separately,and the result shows that both of them can achieve wirespeed reception.At the same time,the analysis and calculation of the delay of the host processing on the interrupt mode and the query mode are given respectively.A message processing time of the host in the query mode is reduced by 65% than the interrupt mode by comparison of the result.Using a query mode can significantly reduce simulation time and improve verification efficiency in a verification scenario with no particular requirements for receiving reports.