Design And Implementation Of Acoustic Parameter Array Preprocessing Algorithm For Echo Cancellation System

With the rapid development of modern science and technology, the technology of underwater target detection is also growing. In order to confront the enemy detecting effectively, anti tracking is also rapid progressing, and echo cancellation technology is the one of anti tracking. To meet the general requirements of portable equipment for the practical application, the single sonar can be replaced by acoustic parametric array (APA), and its unique technical advantages determine the important applications of APA. But in a technical view, APA exchanges larger power and lower efficiency for its unique advantages, thus the key part of APA application is reasonable signal preprocessing algorithm. In the rapid growth of micro-electronics technology, digital signal processing technology has been widely applied in economic construction, national defense science and scientific experiment field and so on,especially the Field Programmable Gate Array (FPGA) possesses powerful parallel processing ability, which can not only improve the processing speed, but also meet the real-time characteristic of high data rate.The main work of this thesis includes design of signal processing platform of echo cancellation system, and implementation of pre-processing algorithm of APA. The pre-processing of signal is a connecting in the whole system for the study of parametric array.In the subject, the KZK equation is deduced, and the quadratic differential approximate solutions of the equation are solved. Three modulation algorithms as pre-processing algorithm of parametric array are discussed, and a modified SSB modulation algorithm is chosen for APA as pre-processing algorithm, which is deduced, discussed and simulated in detail.According to the requirements of the system, appropriate chips and hardware circuit are selected to construct the signal processing platform. The platform uses EP3C40F484C8N of Altera as the center processing chip. This chip has high flexibility, strong parallel processing ability, and low cost, which can meet the requirement of system. In order to ensure the continuous, real-time processing and synchronously output, two SRAMs are placed on the platform as ping-pang cache for gathering data.The programs in the platform are the design as modularity interface, which can ensure the kinds of modules not to effect mutually and convenient to transplant. The entire programs include 4 parts: the controlling A/D module, the data storage module, the pre-processing algorithm module, and the controlling D/A module.The performances of hardware and software at the platform are tested. The amplitude and frequency precision from A/D acquisition, and the drive programs are tested; the data storage module is tested; the output data amplitude and frequency from D/A, the consistency of the kinds of channel, and the drive programs are tested; the functions of pre-processing algorithm programs are tested; the kinds of modules are jointed and tested together, and the correctness of program is verified. The functions of signal processing platform and pre-processing algorithm are verified by APA in the pool of our department.