The Design And Implementation Of Wideband Digital Backend Based On FPGA

The receiver system is an important part of the telescope, and is the determining factor of telescopes performance. The receiver system of a radio telescope is mainly composed of two parts, the analog frontend and the digital backend. The backend primarily consists of ADC which transforms analog signals into digital signals and samples the data in high speed, and the FPGA module in which we can realize the parallel signal processing, as well as high-speed data transmission unit so that the system can download the high speed data. Lately the world's largest radio telescope FAST is under construction in GuiZhou province of China. After the completion of the giant radio telescope, the quantity of data it can receive is enormous, especially for big-scale sky searching project, and the amount of data reaches MB per second.This thesis is aimed at the need of the FAST construction, so we design a super high-speed(3.2GSPS)or,as we can say in another way, a wideband radio telescope data acquisition digital backend. The chip we select is the super high-speed ADC chip produced by American National Semiconductor company for data sampling, together with well-performed FPGA chips ordered from American Xilinx corporation(XC6VLX240T-2FF1759) for parallel processing with big data and at last the system sends the data out through 10 Gbps Ethernet.Specifically, after amplification and modulation in the analog frontend, the signal is sent to the analog filter module, which in total builds the main work of analog front end; then the data will be sent to two pieces of high performance ADC(analog to digital converter) integrated circuit board, as wide as 3.2GHz large bandwidth sampling, 12 bit quantization width. The ADC output through time-sharing multiplexing will be divided into 16 channels and is sent to FPGA board with subsequent poly-phase filtering processing, which implements a parallel 4K-point fast Fourier transform. Consequently, the data is stored into the FPGA board's RAM storage space, then is sent to the backend server cluster system based on CPU(central processing unit) or GPU(graphics processing unit) for storage or processing.After the debugging and testing in laboratory, we proved the digital backend can meet a 0~1.6GHz frequency range of the high-speed signal acquisition ability, the complete system achieves the parallel processing ability of 4096 channels and presents increased expansion of space, and the data output capacity is adjustable.