The Design Of Fully Integrated Readout Circuit Based On GM APD 64×64 Arrays

Laser radar system based on GM-APD array have the ability of single photon detection, long distance detection and works efficient.It has been widely used for rapid recognition of battlefield targets, target tracking,military reconnaissance, warning and so on,which has already become a major projects of the developed countries.But with the continuous expansion of the GM-APD array, the negative impact of the circuit such as non-uniformity, parasitic effect, noise and high power, voltage attenuation has become more and more serious, the design of ROIC readout circuit has been more and more complicated which was seriously limits the application of large scale APD array.This paper has developed a new type of readout circuit, which can be integrated with InGaAs APD 64×64 array. At first,The paper have analysis the difficulty of application for large scale APD array,and then carries on a new system structure of the readout circuit.In order to achieve a balance between the time resolution and range, power consumption of the system,we have choose a two segment TDC. Secondly, we have working on solving the passive effects of non-uniformity, voltage attenuation, and some other non-ideal factors,and design the network of system clock and power. At the end, we have complete the design of pixel array, test bench and system architecture.All the module and the system of the ROIC is simulated through the Cadence EDA tools and fabricated by TSMC 0.35μm standard CMOS process.The working voltage of readout circuit is 3.3V,and the interface’s is 5V.The scale of the APD array is 64×64 with each pixel’s area of 100μm×100μm. The simulation results of ROIC system indicates that the system has achieved a 0.5～2ns timing resolution by adjusting the frequency of TDC. The chip test results indicates that the ROIC is functional,and also can achieve a linearity and stability timing resolution about 2ns when the frequency of TDC was low. The timing resolution could increase as the same of the frequency of TDC.But distribution issues and a clock skew constrained operation to a timing resolution of 2ns. The performance of this chip is close to the international advanced level at 64×64 array.