Analog Iterative Decoding Technique Based On Factor Graph

High-performance channel coding such as LDPC, has been widely used in communications, but the high-performance bring processing complexity and processing power.This problem has become one of the constraints of the communication system terminal miniaturization bottleneck. Analog iterative decoding technology because of its low power consumption and other characteristics processing unit information re-enter the researchers sight. It provides a new choice to further reduce the power consumption of the decoder processing speed.The prototypes realized so far have shown an outstanding improvement in power efficiency and speed comparing with their digital counterparts, with only a little error-correcting performance loss. However, all these implementations are limited to proof-of-concept decoders, with very short block lengths, and thus, they are not suitable for practical applications. So we need to build a more rational behavior model decoder to distribute on the basis of previous studies.Due to the large size of the analog circuit, it is difficult to obtain reliable estimations of the circuit performance in a short time for the analog implementation of high-complexity decoders. Circuit-level simulations are then restricted to small sub-blocks of the overall decoder. Only very small analog decoders may be simulated for a few selected decoding configurations. A more detailed system performance evaluation, particularly in terms of the BER, thus needs to rely on high-level simulation models. It is therefore essential to capture the main characteristics of the analog decoder in sufficient detail and reduce the computational complexity at the same time in order to facilitate simulations for system level specification.In this paper, we propose a mixed behavioral/structural model for the analog implementation of low-density parity-check(LDPC) decoders based on the sum-product algorithm, while taking transistor mismatch effects and circuit dynamic behavior into account. The model, relating transistor-level parameters to system-level specifications, can be used for both estimating the system performance of the analog decoders and providing circuit-optimization guidelines for complex decoder. The model is applied to a(40, 16) linear block code and simulation results demonstrated the model can reliably predict the system performance in a short time. Finally, establish the model and verify that the model can meet the expectations.