Design Of A Small PLC Circuit、Compilation And Communication System

In this paper, a small PLC which has ARM-FPGA architecture was designed, it was consist of ARM and FPGA module, and it make full use of ARM speed processing and FPGA parallel high-speed operation two characteristics, in order to achieve the purpose of improving the efficiency of PLC executes instructions.Hardware, uses the LPC1788 which embedded 512 KB Flash memory, 96 KB SRAM and internal integration CAN controller as the main controller of PLC host, uses ProASIC3 series big capacity chip A3P1000 as main chip of FPGA module, introduces the main module pinout of the PLC host, including ARM external communication circuit module, input and output circuit of FPGA module, and the interface which was designed between ARM and FPGA, then carries on the detailed design to the three part of the circuit, the power supply module, JTAG interface circuit, crystal vibration module which were composition of ARM and FPGA minimum system circuit was also designed,finally uses Altium designer software tool to draw schematic diagram and PCB diagram,and make circuit boards and debugging.Software, including PLC instruction compiler and CAN communication program which PLC host connect to external devices. Combining with the workings of the PLC system, it compiles the static and dynamic compilation of PLC user source program.Static compilation download user program from PC to the PLC host,and preprocess the user program, and designes a InstructTypeDef type structure of the operation code and operands information store, so the source program compiled into new PLC user program code. In a statically compiled code generated by the PLC user program for dynamic compilation, dynamic compilation instructions which was change into " operation code+ logic " will be sent to FPGA which FPGA can recognize. The circular scanning stage of PLC, the CJ, CALL, MC, MCR address jump instructions and other applications instructions was performed by the ARM, the basic logic operation instructions was performed by the FPGA, and the timer timing counting function and counter operation was also completed by FPGA, and finishes the corresponding data configuration between ARM and FPGA.Gives the overall design scheme of PLC communication system, designes the CAN communication protocol, and completes the CAN driver design, and then filtering jamming signal by setting the ID number for multiple devices in the process of sending and receiving information, PLC host finally succeeded in communication between the HMI and PC.The testing part, testing the CAN communication system and instruction compilation system for the small PLC which has ARM- FPGA architecture.Test results showes that the PLC host, PC and HMI of the system is able to use CAN bus to transfer data to be accurately and effectively, the PLC source program which was composed of basic instructions and application is compiled for the correct funtion.