Design Of Total Controller Of Small PLC Based On FPGA

PLC has been widely used in every field,especially in the field of industrial automation control. The topic for the ARM-FPGA composed of small PLC system, hard connection control circuit designed by FPGA, Small total FPGA module of PLC controller is designed.In this paper, four parts is designed by FPGA, the total controller with independent control functions, ARM and FPGA interface circuit of dual port RAM, input module and output module.The main results were obtained in the following:(1) Design of total controller based on FPGA. The total controller comprised of 10 circuit module, the pulse distributor, edge detecting ciecuit, interrupt notification response module, address judgment circuit,data transmission circuit, decoding circuit, input module control circuit, output module control circuit, logic control circuit, C port control circuit, B port control circuit and INT1 interrupt control circuit. The total controller responsed the interrupt and reads command word to decode, when detecting the interrupt signals of INT0 sended by ARM. According to the result of decoding result, the total controller selected a function module by the address bus and sent commands and operands by data bus. The total controller sent a corresponding timing control signal according to the timing requirements of the function module.The function module which is needed to return the results sent results to the total controller in accordance with the timing of execution of instructions. In the internal timing control, total controller read the results and then wrote in the appropriate memory cell of dual-port RAM.(2) Design a dual-port RAM with arbitration function which the data bus is not equal, realize the data share of two ports. When two ports read or write the same address at the same time, A port had the priority to read and write.(3) Design the input circuit module with acquisition and high-speed data acquisition function. Under the control of the total controller of timing control circuit, the input module selected by the address bus, completed independently 64_bit state acquisition of the input port of PLC with the control of the chip select signal and read signal.(4) Design the output circuit module with output refresh and high-speed refresh function. Set four module addresses in the internal output module, and the output module was selected by the address bus. The state of Y image area of dual-port RAM was refresh to the output terminals of PLC independently.(5) Made the experiment scheme, after the function simulation, timing simulation on the software, layout and pin assignment, download the control program to ProASIC3 A3P1000 of Actel company,and then do the board-level test, verify the feasibility of the designed circuit.