Research On The Circuit Partitioning Algorithm Of Embryonic Bio-inspired Hardware

Embryonic electronics(Embryonics in short) is a digital integrated circuit with the capability of autonomously repairing circuit faults. Inspired from the natrual redundant architecture of cells in living organisms, Embryonics is design to have a cellular array, where each Cell has the same hardware resources. Based on the generalized hardware design, working Cells can be replaced immediately by redandunt Cells when circuit faults are detected, and in this way, we can save the cost of off-line reparing. However, 2 difficult problems of Embrynics are still remained: the large wiring of cellular array increases the overhead of chip area, and the rising propagation delay of critical path makes Embryonics hard to meet timing constrain.Based on the hypergraph theory, this paper firstly put forwards 2 algorithms to solve these 2 problems respectively: Min Wire algorithm for area optimization and Max Freq algorithm for timing optimization. These two algorithms can reduce the wiring quantity, and decrease the critical path delay. The partitioning results of circuits in ISCAS89 benchmark shows that Min Wire and Max Freq have the best perfomance in aspects of wirig reducion and timing constrain, c omparing with the conventional algorithms as h Metis, FM, VPack.Since the final objective of Embryonics is to realize the self-repairable application specific integrated circuit with large scale, the implementation on silicon should trade off the area optimization and timing constain. Combining advantages of Min Wire and Max Freq, this paper provides a synthetical algorithm, Best Perf, to reduce the chip area and make the cellular array satisfy the timing constrain in the same time. In order to test the performance of our algorithms, we apply Min Wire, Max Freq, Best Perf and 3 traditional partitioning algorithms to the Cell array partitioning problem of the transmitter in Bio RS232, a bio-inspired hardware platform. The synthesis reports of Design Compiler shows the results of wiring area, critical path, and memory ultilization of the corresponding cellular array of each partitioning algorithm. Comparing with other algorithms, Best Perf has the best overall perfomance.