Design Of A RZ Analog Demodulation Circuits Based On CMOS Technology

With the rapid development of economic,all kinds of comunication equipments building and people’s requirements of high quality and high speed of the information transmission,make the peoblem of high spectrum efficiency become a topic of concren. EBPSK modulation is a highly efficient modulation way for return to zero code,and this paper designs a hardware demodulation circuit for the three special modulation methods of EBPSK.The circuit of a RZ analog demodulation based on CMOS technology, is mainly composed of single to dual converter, mixer, low-pass filter, single to dual converter, inverters and D flip-flop. In order to improve phase matching of differential signals in the high frequency, the circuit of single to dual converter (SDC) joined the compensation capacitance;It is a good method to improve the third intercept point of mixer by putting the pseudo differential structure to the circuit of Gilbert module in parellel. Low pass filter adopts transconductance Gm-C structure. Not only the cut off frequency can be adjusted,but aslo reduce the area and power consumption of the system. In order to adpot D flip-flop to sample signals, this paper designed a single to dual converter which is consisted of current mirror and inverters.The whole circuits can demodulate three kinds of the modulation signals by using two group of inverters,and get different flip level through changing the breadth length ratio between PMOS and NMOS.The D flip-flop of this paper is improved from the tradition TSPC structure and use the falling edge trigger mode,which can reduce the number of devices and the area of the chip.In this paper, TSMC 0.18um CMOS technology is used to complete the whole circuits and the area of the chip is 0.55mm×0.756mm. The post-simulation results show that the output voltage amplitude is about 1.8 V when the power supply is 1.8V and the load is high.This circuit can demodulate the three spcial signals and the duty ratio of return to zero code can be choosed from 10% to 90%,carrier frequency is from 10MHz to 2.4GHz. The whole power consumption is 21.37mW in TT process corner and meet the design target.