Research And Implementation On ADC SNR Improving Technology

In analog-digital system, the precision and speed of the analog digital converter (ADC) has been the key indicators of system performance. With the high speed development of the application and the demand, the analog digital converter has been pursuing with faster speed and higher accuracy continuously. With the technique this article researches, the signal to noise ratio of the corresponding frequency band can be improved with less data bits under condition of narrow band and can be same signal to noise ratio with high data bits. It is important to application system such as communication receiver.This paper analyzes the operating principle of the technology of SNR improving under condition of fewer bits. After that, the paper puts forward the implementation scheme and mathematical model of the technology of SNR improving under condition of fewer bits. This paper, using the MATLAB platform, constructs the simulation platform of finding suitable filter model. And then, with the simulation platform, combining with the measurements of the AD converter, this paper does a great deal of simulation work for the algorithm system. Through the model simulation, the difference between the linear hypothesis and the actual model is solved and practical system solution is found. With the method of asymmetrical zero, this paper finds four filter models suitable for different application scenarios. Under the condition of 250MSps sampling rate, a filter model with four different bandwidths is realized, including 11 bit output 90MHz bandwidth,9bit output 40MHz bandwidth and 9bit output 45MHz bandwidth. A dual band transmission of dual 45MHz bandwidth model is realized innovatively. If only 25%is required, the system can realize the compression from 14bit to 6bit.Then, in FPGA hardware platform, using hardware description language Verilog, hardware structure of the system is realized. In FPGA designs, through designing zero delay high speed FIR filter structure, the paper solves the timing problems in the hardware feedback loop. Through a large number of simulations for the word length of filter coefficients, the paper finds suitable fixed-point coefficients which give considerations between hardware resources and operational precision. Through human intervention layout, optimization according to the characteristics of the filter coefficient and adjusting the filter structure and other methods, this paper solves the problem of long feedback delay, redundant multiply-add operation, which influence on the speed of hardware. The hardware is fully realized under the 250MSps sampling rate with 4 operating modes of low bit rate SNR improving system. In the actual test on test platform of ADC, the result shows that the technology can reach the expected target. And the code of Verilog hardware description language can be applied to ASIC design. It is important to ADC design.