Parallelization Design And Hardware Implementation Of Correlation And Symmetric FIR Algorithm

Reconfigurable processor has been the research and application hot spot of the processor recently, it usually choose functional units that can be configured dynamically, then map the algorithm to the calculate engine. Reconfigurable architecture can greatly improve the system flexibility and the utilization rate of resources, and maintain the superior performance advantages from application-specific integrated circuit at the same time. Because of the advantages such as flexibility and performance, reconfigurable processor has become the first selection of many high-end applications. This paper gives a kind of reconfigurable application-specific processor architecture that can be integrated in the heterogeneous multi-core SoC system. The internal main module, resource structure and system parameters are introduced. The topology structure and interconnection of the basic computing unit can be changed by coarse-grained static configuration, while hardware acceleration is achieved by resource reuse.The main function of the processor is to implement several digital signal processing algorithms such as FIR, correlation, FFT and matrix computing. This paper mainly studies the hardware implementation of three algorithms, namely self-correlation, cross-correlation and symmetric FIR. First of all, according to the algorithm features of multiply-accumulate, a kind of multiply-accumulator is designed that suits the algorithm characteristics and meets the project requirements. Connecting with the computing resources and storage resources, the parallelism is set as four. To solve the task assignment problem the nonuniformity brings in, this paper puts forward a kind of parallel partitioning strategy based on load balancing, makes load distribution consistent and reduces system running time as much as possible. Due to the Inseparability of source vector and limited storage resources, different vector corresponding to different parallelism and realization method. To cover the length demand from 16 to 128K, this paper puts forward three kinds of hardware design and implementation. Symmetric FIR algorithm can achieve arbitrary point hardware parallelization by two-dimensional segmentation technology, this method can solve the problems of data segmentation and data storage DMA transmission brings in, and the data segmentation problem because of the limited memory capacity in the case of very long vector. This article also gives the waveform graph of key module and the simulation results of sets of feature points to prove that the performance objective meet the requirement of real-time processing.Finally, the paper introduces three kinds of test platform and verification methods:traditional test platform, the FPGA prototype chip verification and the automation test platform based on UVM verification methodology. Then the specific test content and coverage analysis based on the RTL design of the three algorithms are presented.