Research On Wideband Frequency Synthesis Technology Based On Cascaded Offset Phase-Locked Loop

Frequency synthesizers are key components in virtually all electronic systems. Wideband frequency synthesizers with low phase noise and high frequency resolution can be widely used in radar, communication and electronic test and measurement systems. In order to achieve the low phase noise and high frequency resolution performance, wideband frequency synthesizers always use all of the three basic frequency synthesis techniques, including direct analog frequency synthesis, direct digital synthesis(DDS) and indirect phase-locked loop(PLL) frequency synthesis.In this thesis, a cascaded-offset phase-locked loop is designed to improve the phase noise performance of the wideband frequency synthesizer. By introducing cascaded mixers in the feedback path of the phase-locked loop, the frequency divider in the feedback path of the phase-locked loop is eliminated, which dramatically reduces in-band phase noise. A circuit is designed to verify the performance of cascaded-offset phase-locked loop with a wideband YIG Tuned Oscillator(YTO). When the reference frequency is fixed at 1600 MHz, the phase detector frequency is fixed at 25 MHz and a frequency set of 66 points from 1950 MHz to 5225 MHz with 50 MHz step can be able to output from the designed cascaded offset phase-locked loop. A multiplier chain was designed to achieve the 1600 MHz single-point reference source from a 100 MHz Oven Controlled Crystal Oscillator(OCXO). The measured phase noise at 100 kHz frequency offset in the loop bandwidth is-118 dBc/Hz when the output frequency is set to 5225 MHz.In order to achieve the fine frequency resolution performance, a 1706 MHz to 1750 MHz narrow-band frequency synthesizer with frequency resolution less than 0.1 Hz is designed as the reference source of the cascaded offset phase-locked loop. A wideband frequency synthesizer with output frequency range of 2106 MHz to 5670 MHz and frequency resolution less than 1 Hz is obtained when the two modules are connected together along with corresponding automatic configuration algorithm. The reference source of the designed reference loop is the 1600 MHz signal from the X16 multiplier chain. In the reference loop, mixer-divider method is used to alleviate the spurs of the direct digital synthesizer(DDS), and offset phase-locked loop technique is used to improve the phase noise performance. When the reference loop output frequency is set to 1728 MHz, the measured phase noise at 10 kHz and 100 kHz frequency offset in the loop bandwidth is-115 dBc/Hz and-121 dBc/Hz respectively. The measured phase noise of the wideband frequency synthesizer based on cascaded offset phase-locked loop at 10 kHz frequency offset is-113 d Bc/Hz and-110 dBc/Hz when the output frequency is set to 2123.125 GHz and 5 GHz respectively.