The Design Of Error Field Active Control Prototype System Of Keda Torus EXperiment (KTX)

Keda Torus eXperiment (KTX) is designed by USTC, which is the first large RFP experiment device. RFP configuration is characterized by multiple MHD modes existing simultaneously. The error field surround the Double-C slit zone limits the plasma current and the increase of discharge duration, which may cause severe plasma-wall interaction and premature termination of plasma discharging. For the sake of enlonging the plasma discharge duration and improve the magnetic confinement performance, it is necessary to develop active control technology and suppress the error field.This paper mainly researches the design of active control system based on PID technology, which the system can be used to suppress the error field and improve the plasma discharge. The system can be feedback controlled at the same time in KTX, which can efficiently control the error field. This paper is divided into the following chapters:The first chapter is the introduction, briefly introduces the physics background of KTX active control system and the concept of design.The second chapter illustrates the demand of the error field active control system in KTX and the physical meaning. In addition, this chapter explains the function and installing position of the active control system in KTX.The third chapter proposes the hardware and software design of the error field active control system in KTX. In addition, the chapter gives the description of the PID control system working mode, software and hardware implementation based on the architecture of FPGA+STM32.The fourth chapter introduces the selection of chips, hardware design and PCB layout of the error field active control system in KTX. In this chapter, the design of analog amplifier circuit and the sampling circuit is directly related to the calculation result of the final control voltage. In the design, the small signal is transmitted through the shielded twisted pair, and the output of the two-stage amplifier circuit is connect with the high precision ADC chip sampling pins, which can improve SNR of the system.The fifth chapter describes implementations of the FPGA logic design for error field control system, including data acquisition, framing transmission, command parsing, ADC interface control, DAC update.The sixth chapter describes the function of the MCU in the control system and introduces the implementation of network data transmission software. It describes the key technical difficulties in transplanting LwIP network protocols into STM32. In addition, the chapter describes the implementation of the SPI communication between FPGA and STM32.The seventh chapter makes the conclusion of the work in the whole paper and points out the innovation points of the research, shortcomings of the active control system in KTX, and improvements of further research.