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The Analysis And Design Of An Efficiency Chip With Large Current Capacity

Posted on:2017-01-10Degree:MasterType:Thesis
Country:ChinaCandidate:C WanFull Text:PDF
GTID:2308330485488363Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the human steps forward into the 21 st century, the speed of the development of electronic information industry also steps on a new stage. More and more electronic technology products come into the people’s everyday life. To personal family life, to the industrial production, national defense, there is great influence by the electronic information industry and has a great and profound changes. Switching power supply is also moving in the direction of high current density and high efficiency.In this paper, we design a kind of high current and low power waste DCDC BUCK chip, which uses the PWM mode, and the internal oscillator frequency is 500 KHz. The input voltage ranges from 5.5V to 60 V. The power switch transistor is integrated in chip internally. The output current is up to 3A. In the typical application of 5V2 A, the whole chip efficiency reaches 87%. This paper first briefly introduce the basic principle and the basic situation of switch power circuit of switching power supply. Analyzes the two factors which can affect the chip maximum output current and static power waste structure: slope compensation circuit and drive module. In view of the problem of slope compensation, the improved methods of linear slope compensation and anti-slope compensation are proposed. A structure of high speed and low power waste circuit driver module is proposed. From finding a way to solve the problem to the mathematical model calculating to building the actual circuit of the two circuits are described in detail. Finally we decide to adopt PWM modulation mode, peak current control mode, combined with linear slope compensation, anti-slope compensation and a drive circuit with special structure in this design.The Shang Hua 2 um BJT process is used to simulate for testing the circuit performance. And the result shows that the traditional structure improves the current flow limit and improves the efficiency of the whole chip. The final simulation data shows that the design achieves the goals we are looking forward at first.
Keywords/Search Tags:PWM, Slope-compensation, Driver, Buck structure
PDF Full Text Request
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