A High-performance Implementation Of AES Algorithm Based On ZYNQ

AES (Advanced Encryption Standard), also known as Rijndael cipher in cryptography, is a block encryption standard adopted by the US federal government and used to replace the original DES (Data Encryption Standard). It has been widely analyzed and used around the world. AES was published by the US National Institute of Standards and Technology (NIST) in 2001 and became an effective standard on May 26, 2002. It has become one of the most popular symmetric key algorithms.There are various methods to implement AES algorithm:software implementation is more flexible and versatile. It can be easily applied to a variety of occasions; hardware implementation can achieve higher performance to meet the requirements of many applications. This paper uses a new SoC-ZYNQ, one of Xilinx devices, to implement the AES algorithm. ZYNQ is a device of dual-core architecture. Its PS side can be used to run an operating system, execute a software program and carry out a variety of tasks. Its PL side can be used to optimize and accelerate the AES algorithm, which is called by the PS side. The two sides transfer data via a high-performance AXI bus. Because of the advantages of ZYNQ architecture, this design achieves the versatility of software implementation and the high performance of hardware implementation compared with the conventional designs.This paper studies the structure of the AES algorithm, and analyzes the multi-use sub-module and optimizes the key module such as SubBytes and MixColumns. This paper uses the VIVADO development tools and the VHDL hardware description language to complete design entry, functional testing, timing simulation. The AES algorithm is then packaged as an IP core which meets the AXI bus protocol for design reuse. The AES algorithm IP can be integrated into the PL side, as an AXI stream module called by the software program on the PS side. Based on the success of simulating each module, the AES algorithm IP is integrated into the systems project and tested on the ZedBoard. This design has the same result as the AES calculation tool. Finally, the AES algorithm performance analysis and resource utilization are given, which show the excellent performance of this design. This design uses the 1844 Slice LUTs,803 Slice Registers and two Block RAMs. Its encryption throughput reaches 1828Mbps, and decryption throughput reaches 1066Mbps, which meets the requirements of most applications.