Bandgap Voltage Reference Design With Process Variations

As the feature size of CMOS technology is scaled down, device mismatch and process tolerance will lead to deviation in integrated circuit (IC) and significantly impact manufacturing cost by decreasing yield. Therefore, Design for Manufacturability (DFM) due to process deviation has become one of key challenges in IC design and manufacturing.This thesis starts from discussion about a main source of process deviation random dopant fluctuations (RDF), leading to decreasing yield. It is studied theoretically that RDF will cause the deviation of threshold voltage and current gain factor. As a result, the current mismatch model will be affected by RDF. Then in a detailed study of existing mismatch models, a mismatch model based on CSMC 0.5 μm is proposed.The voltage reference source is the main module of the mixed signal LED driver chip, and its performance is the important factor that will influence the whole system. A structure fitting for the LED driver chip in standard CMOS process is selected after studying in several voltage reference circuits. Then this thesis introduces the corresponding mismatch model to reduce the effect of process deviation from three aspects:parameters, schematic and layout.Finally, the design is verified by HSPICE simulation and chip test:HSPICE simulation shows that the output of the bandgap reference circuit is 1.2318±5×10-3V in CSMC 0.5μm technology; The design is applied in 3 channels LED driver chips and test results indicate that the yield reaches to 96.8%, while the chips that meet the output current requirements of 18±0.5mA account for above 99.6%.