| The research issue of this thesis comes from "Wireless Speech Intercept System" project in 13 th institution of CETC(China electronics technology group corporation), which need to receive, demodulate, decode, store and play the speech signal with PCM coded, carrier frequency from 450 MHz to 460 MHz, data rate of 200 KHz, BPSK or DBPSK modulated. We have to research and design a wireless receiver with high sensitivity, powerful antinoise ability and able to deal with multiple demodulation methods, with that background.We investigated in depth to the existed wireless communication technologies, design and implemented a digital intermediate frequency wireless receiver system based on SDR(software defined radio). The system contains three parts: part one is RFAF(radio frequence analog front end), which contains antenna, LNA(low noise amplifier), BPF(band pass filter), frequency source, down-conversion mixer, intermediate frequency amplifier etc, this part receive RF signal and amplifying, filtering, mixing it, then generate a IF(intermediate frequency) signal with fixed frequence and amplitude for the subsequent signal processing; part two is digital intermediate frequency processing module, which contains ADC(analog digital converter), DAC(digital analog converter), digital signal processor like DSP or FPGA, this part sampling IF signal, demodulating and decoding it by digital signal processing technology; part three is interface and PC processing module, this part provides interfaces between receiver and PC, store and analysis the speech signal if necessary, we need to denoise the speech signal we received in this thesis.During the design process, we ran system level simulation as feasibility test with simulink, RF simulation and optimization with ADS, then designed PCB board with Altium Designer, ran FPGA simulation and demodulation algorithm optimization with modelsim and matlab. Finally we did hardware debugging and experiments with kinds of tools like SignalTap. According to simulation and hardware test result, the digital intermediate frequency wireless receiver designed in this thesis reach the following specifications: RF part: receive sensitivity to-100 dB, phase noise outside 1KHz lower than-60 dBc, time for changing channels lower than 60us; digital IF part:lowest SNR of input signal is 5dB, the max frequency of FPGA higher than 200MHz; the improved spectral subtract denoise program is able to enhance the speech we received, decrease the user’s auditory fatigue and improve the speech signal intelligibility obviously in practical application. |
