Design Of Low-power 16-bit Resolution Delta Sigma ADC

Driven by the speed demand of digital circuits, the CMOS transistor feature size has been scaling-down, which has led to the reduced supply voltage and the degraded device characteristics. Limited by non-idealities of circuits, traditional Nyquist ADCs have difficulties in high-resolution transition, while Delta Sigma ADCs, which adopts oversampling and noise shaping techniques, have still reached high resolution because of its lower demand for the performance of circuits. With the popularization of the portable electronic equipment and the development of digital integrated circuits, out of the consideration of stand-by time, heat radiation, chip package, et al, how to reduce a climbing system power has become a hot research topic.By the analysis of low-power Delta Sigma ADC design techniques,system and circuits, and the comparision of the various characteristics of different structures, such as power consumption, the design adopts a fourth-order single-loop 1-Bit quantization structure realized with double-sampled swicthed circuits. Different from other structures, it keeps insenstive to the non-idealities of circuits and the output swing of integrators in it is lower, which is beneficial to low-power design. The modulator has been realized with the double-sampling switched-capacitor circuits, which can double the oversampling ratio and without the extra demand for circuit performance, it can increase the resolution of this system by 4-bit. The gain-enhanced current mirror amplifier with class-AB output stage has been applied in the first integrator which usually decides the power consumption of a system, which can greatly reduce the power. At the same time,the high-precision current source has been adopted to offer current bias for the system to lower the effect on the performance of the system brought by the variations of technology, supply voltage and temperature. The modulator is clocked at 3.072 MHz and sampled at 6.144 MHz, the signal bandwidth is 24 k Hz and the over sampling ratio is 128. The decimation filter is realized by fifth-order CIC filter with a clock frequency of 6.144 MHz and a down sampling ratio of 128.Employing SMIC 0.18μm CMOS technology, the circuit and layout of every module in the Delta Sigma ADC have been designed with care. The simulation result shows that total power consumption of the analog core part in this system has been 0.606 m W, while that of the digital part has been 0.291 m W. The transistor-level simulation shows that the proposed structure has achieved 104.63 d B-SNR.