Study On 于LUT-MSMP Model For Digital Predistortion With Low Complexity

With the development of Digital Predistortion(DPD) techniques, the adaptive DPD based on Memory Polynomial(MP) model becomes the most popular linearization techniques for power amplifiers(PAs). DPD based on MP model becomes a hot topic because of its high compensation precision, tracking adaptability and easy implementation.For better performance of behavior modeling and predistortion for power amplifiers, the nonlinearity order and memory depth of MP model should be set very large. The complexity of the models will be increased and the parameter extracting algorithm also becomes more complex. In order to solve the conflict between complexity and performance, a Look-Up Table cascade Multi-Stage Memory Polynomial(LUT-MSMP) model was proposed. The proposed model showed good performance of behavior modeling for Pas with low complexity. The pre-distorter constructed on this model could achieve a better linearity performance with low complexity.For validation purpose, the proposed LUT-MSMP model was implemented in Matlab/ Simulink platform. The amplifier based on Laterally Diffused Metal Oxide Semiconductor(LDMOS) from NXP Semiconductor was the simulation object in the experiment. The accuracy of behavior modeling was measured by Normalized Mean Square Error(NMSE). Compared to the widely used MP model, the LUT-MSMP model was demonstrated to achieve a comparable accuracy with almost 50% reduction in complexity and reduction of 15 parameters. Compared to the Forward Twin Nonlinear Two-Box(FTNTB) model, the proposed model had approximately 16% reduction in complexity and reduced 3 parameters. The experimental results showed that the proposed model can achieve an NMSE of-39.27 d B.Secondly, in order to validate the performance of the pre-distorter based on the proposed model, the simulation system was driven by the Wideband Code Division Multiple Access(WCDMA) signal with a bandwidth of 5MHz.The measured Adjacent Channel Power Ratio(ACPR) from the center frequency at an offset of-5MHz and +5MHz achieved-53.64 d B and-53.56 d B respectively in the output signal. Compared to the MP model, the proposed model had an improvement of 5 d B in ACPR and reduction of 26.7% in complexity. Compared to the FTNTB model, the proposed model had improvement of 1.2 d B in ACPR and reduction of 8% in complexity.Finally, the pre-distorter was implemented in Field Programmable Gate Array(FPGA) to evaluate the resource utilization in actual circuit. It is reported that the pre-distorter based on the proposed model consumed 2785 Logical Elements and 3072 RAM bits.The research results in this thesis will be a new reference model for the modeling of power amplifier in low complexity and a reference design for digital pre-distorter with high performance and low complexity.