Research And Design On SoC Architecture Optimization

With the rapid growth of very large scale integration(VLSI), a design space exploration problem has been raised with an attempt to reduce time and resources for designing an optimal integrated circuit(IC) The system performance is mainly contributed by the system architecture. In this thesis, we present an optimization methodology on system-level, which contains anovel performance analysis model and a heuristic method for partitioning arbitrary devices. In addition, most of System-on-Chips(SoCs) are based on AMBA bus, so this thesis focuses on the optimization of resources configuration within AMBA bus.This paper makes a general research on the main stream system architecture of multi-core processors; the bus configuration of AMBA is discussed in detail. On the bases of the former research, this thesis established an optimal design method to the overall system structure. In order to reduce system communication delay, the simulation model and analysis model are analyzed simultaneously. In detail, the efficiency of the paralleled operating system is increased by allocating the occupation of system resources efficiently. The work of the thesis is included as follow. 1) In order to know the communication status of the system under different driving source, the main system structure of current multi-core processor is researched. This structure can also verify the effectiveness of the optimal algorithm. 2) A delay detection IP core is designed, which is utilized to monitor the communication situation among master and slave devices. The communication situation includes the size of communication traffic of every master device, the clock cycles of occupying bus for every master device and the bus arbitration. 3) A system analysis model is established, by which the corresponding rule to optimize system architecture can be concluded. 4) The communication data graph and communication matrix is extracted from the analysis model, which is used as the initial conditions for algorithm optimization. The proposed algorithm can ensure the high efficiency of bus work by reducing the communication traffic of transfer bridge among different buses.In order to validate the proposed system architecture optimization algorithm, this thesis designs five optimization verifications by using single-bus architecture, two-bus architecture and four-bus architecture. The verifications show the simplify operability and high efficiency of the optimization algorithm. Obviously, there is a sharp decline on the latency of the system.