The Analysis And Design Of High-voltage Sensefet

Bypass Diodes were mainly used in photovoltaic solar array in the bypass switch. When the hotspots being caused by sun’s shadow or other abnormalities occurred in the photovoltaic cell, current will flow through the bypass diodes without being blocked.Comparing to traditional type P-N junction and Schottky bypass diodes, new intelligent bypass diodes have lower forward conduction voltage drop, smaller reverse leakage current, lower power dissipation, longer life and more stable properties and thus becoming research focus. New intelligent bypass diodes contain an ultra-low forward conduction voltage drop power VDMOS device and a gate driving circuit. The main research of this thesis is about the design of VDMOS device of intelligent bypass diodes, and the main works are as follows.After the basic study of theory analysis on the working principle and electric properties, according to the requirements of the scenario of VDMOS device bypass diodes, VDMOS cell with sorting grids structure is presented. By eliminating routine JFET region of VDMOS structure of the gate electrode covering, ultra-low gate-drain capacitance has been achieved. Moreover, using ion implantation technique in JFET region and increaseing the number of cells per unit, we could further reduce on-resistance and gate capacitance of the device.Considering the technological conditions of program partners, we designed the structure and process flow of the cell and terminal area of ultra-low forward conduction voltage drop VDMOS device. We simulated and optimized the device process parameters and structure parameters using Tsuprem4 and Medici and comprehensively and systematically studied the effects of physical parameters of the epitaxial layer, JFET area, pbody area and N+ source region on the electrical properties of VDMOS. On the base, the optimums device process and structure parameters of cell and terminal area have been achieved. To finally obtain the index of ultra low forward voltage drop VDMOS device: reverse voltage is 40 V, current capability is 16 A, the threshold voltage is 1-2 V, conduction voltage drop is 48 mV, the leakage current is 10 μA, the gate capacitor is 1.7 nF.According to the optimum results, we finished the back-end design of the VDMOS device layout using L-Edit, and completed the design of ultra-low forward conduction voltage drop VDMOS device.