Design And Experimental Study On RF LDMOS Transistor Of S Band

The rapid development of modern mobile communications, for high-quality, high-volume information transmission promoted RF LDMOS to a higher frequency and wider bandwidth applications. The same time it also takes a serious challenge for design. Due to the presence of R&D capability in domestic for RF LDMOS behind abroad, to carry out research and design of RF LDMOS has far-reaching significance for defense and national economy.In this paper, the S-band RF LDMOS devices was designed and modeled, which used a single-source field plate shield and trench sinker on source active region. This structure reduces the device area. First, based on the structure, the optimal design and simulation of the structure parameters are made. Drawn the layout of the device with Cadence and taped out in HHGRACE. The device, which gate length and width are 0.4μm and 140μm respectively, obtained 65 V of breakdown voltage, threshold voltage of 1.5V and the cutoff frequency of 9GHz. The device with gate width of 1mm, obtain 3dB gain compression point of 30.1dBm, the maximum gain of 20.1dB and maximum efficiency 53.1%, the power density of 1W / mm.Based on the test data, the model for device of dual-fingers was built using a nonlinear model of Angelov. In the DC IV model fit, the fit factor P1 associated with the drain voltage Vds, and get a better fitting results. Nonlinear capacitance model analysis, due to the impact of RF LDMOS structure and the bias of the drain-source capacitance Cds, and therefore also the model fitting Cds. Finally, the model is embedded into the ADS, has been large-signal model of dual-fingers of device.In this paper, after the device design, simulation, tape-out and test, a better performance of the RF LDMOS devices was obtained. The establishment of a large-signal model of small gate width of the device, and laid a good foundation for future modeling of large power RF LDMOS devices.