The Design And Implementation Of Color Image High-speed Acquisition System Based On FPGA And Area CCD

Industrial cameras for field automation equipment design, pattern recognition, artificial intelligence, machine vision systems, has very important significance, in the selection process of industrial cameras not only to consider the specific requirements applicable to detect the environment and stability, and the need to consider their Effect of the specific application case of the overall system cost. With the image acquisition that require resolution, pixel values, image size and other indicators on the increasingly high, in the process of image transmission, image processing, transmission bandwidth, processing speed is also put forward higher requirements. In some require multiple cameras simultaneously to capture images of the occasion, the use of traditional means need to use multiple frame grabbers as well as multiple computers, the more the number of cameras, transmission part of the cost is greatly increased. To solve the problems above, the miniaturization and economic issues into the premise, designed a planar array of FPGA-based high-speed CCD color image acquisition system.This thesis describes the development status and trends of domestic and foreign industrial video image acquisition and machine vision, based on the research of the works area array CCD sensor, analyzes the color image restoration algorithm principle and its implementation in hardware approach, designed the area CCD image acquisition system based on FPGA.The key point of this research are: 1 for the complex array CCD sensor drive timing understand and use FPGA generate a corresponding timing waveforms; two front-end data cache and pipeline transmission, parallel processing, based sopc of USB2.0.. communication and data transfer protocol developed with the host computer; 3 for AD chip configuration registers and their impact on image quality.Use in the design process of top-down design approach, a reasonable division of the system modules, each module is divided on the synergy between the various modules communicate with each other have carried out a detailed design, fully taking into account the characteristics of parallel programmable logic device, pay attention to the requirements of the code style, consider the portability across platforms, and maximize overall system performance.In this thesis, for the completion of the hardware platform and the logical design of two parts, the hardware platform is divided into two parts, one for the CCD image acquisition board, mainly CCD chip, CCD drive circuit, and the other part of the FPGA core board, including the FPGA chip, A / D chips, SDRAM memory modules and USB2.0 interface and its peripheral circuits. Hardware logic by Verilog hardware description language, in accordance with the system functions into the CCD driver module, A / D driver module, SDRAM cache module, USB transmission module, an image module algorithm.Finally, complete the test of the system, using modelsim completed for CCD driver, A / D driver emulation, use the PC to complete the image of the show, to get a good result, to achieve the desired subject objectives.