Research On Digital Self-interference Time-frequency Synchronization For Co-frequency Co-time Full Duplex With LTE

Generally, wireless communication systems employ either a time-division or frequency-division approach for transmission and reception of wireless signals. It results in a reduction in temporal or spectral resources. Nowadays, with the growing demand for wireless data business, the spectrum resources become more and more tight. Thus, people pay more special attention on co-frequency co-time full duplex communication.However, to receive and transmit on the same frequency band at the same time, the local sending signal will be strong interference to the local receiving one. Nowadays, many researchers have used digital self-interference cancellation in experiment for full duplex communications. There is no prior work on the effect that carrier frequency and symbol timing offsets can do to digital self-interference cancellation.Thus, this thesis studies the theory of time and frequency synchronization in digital self-interference cancellation. Design a pilot-aided self-interference synchronization method. Implement the synchronization algorithm on the FPGA platform. Test and analyze the function and performance on the scenario of our full duplex wireless communication system. The main contributions of the thesis are as follows.Firstly, a pilot-aided self-interference synchronization method is analyzed. Based on the LTE signal of 20 MHz bandwidth, the thesis studies and simulates the impact of carrier frequency and symbol timing errors on the performance of digital self-interference cancellation. The result shows that with the impact of symbol timing errors from-1 to 20 symbols, the performance loss of digital self-interference cancellation is less than 3dB and the performance loss of digital self-interference cancellation is less than 1dB with the impact of 15 Hz carrier frequency errors.Then, a pilot-aided self-interference synchronization method is designed and implemented. Based on the LTE frame structure, we design and simulate the key algorithm. At the same time, the method satisfies the specification that the performance loss of digital self-interference cancelation using the synchronization method is less than 3dB. What’s more, implement the algorithm on the FPGA platform including software framework, the main process of some key sub-modules and so on.Finally, based on our full duplex wireless communication platform, the function and performance of the synchronization method are tested and analyzed. The experiments on real notes show that the pilot-aided self-interference synchronization software can be applied to the system of two nodes exchanging information with each other on the same frequency band at the same time. Besides, when the bit error rate is at the level of 10-7, it has about 3dB loss compared to the perfect synchronization fixed point simulation result.In this thesis, a pilot-aided self-interference synchronization method is designed which can be applied to a full duplex wireless communication system with two nodes. The synchronization method can also provide theoretical and engineering reference to the further exploration.