The 802.11 working grouphave released b/a/g/n and several other versions of the protocol, now the dominant is 802.11 n, it can provide users with a maximum 600 Mbps data transmission rate, but it also can’t satisfy people’s needs, so 802.11 ac was born. The 802.11 ac is working in the relatively less crowded 5GHz bands,according to the theory its data transmission rate can reach 7Gbps. Whether it is 802.11 n or the next generation of high speed Wi-Fi, it plays an important role in our life.Based on the background of Wi-Fi technology, in this thesis, the channel estimation in wireless communication, signal detection technology and the core module of detection algorithm’s(matrix inversion module) implementation on FPGA have been studied.Firstly, the process of Wi-Fi development are briefly introduced,the Wi-Fi physical layer frame format are analyzed and discussed,and the key technology of the physical layer are briefly introduced.In the study of channel estimation in OFDM systems, this thesis discusses and analyzes thecommonly used wireless channel estimation techniques such as LS, MMSE, LMMSE and so on. Based on the OFDM channel estimation, the MIMO channel estimation techniques are analyzed and studied in detail, we discussed the FDM TDM CDM pilot structure, and simulated them on the condition of the residential channel model in Wi-Fi,at last we made the improvement. On the condition of the same power and the same resources of pilot with 4 and 6repeated sequence, known from the simulation results that the MSE of channel estimation improvedabout 4dBcompare with the original method, about 8dB can improved if combined with filtering algorithm.This paper also studied the commonly used MIMO detection algorithms such as ML, ZF, MMSE and so on, the simulations show that ML is the best algorithm.On the background of the research of MIMO detection algorithms, we studied the implementaion of matrix inversion moduleon FPGA.Firstly, we discussed the algorithm of matrix inversion, and then choose the best algorithmwhich is most suitable for our application scenario. Finally, we designed the 4*4 and 8*8 complex matrix inverse curciut by FPGA. With 130Minv/s and 10Minv/s throughput, the former meet the requirement, but the later needs improvement to meet the requirement. |