Design Optimization And Experimental Study Of 1700V SiC Power DMOSfet

Owing to the high critical electric field, high thermal conductivity, high electron saturated drift velocity and high radiation resistance, Silicon Carbide has been one of research hot spots in the field of power semiconducts throughout the world. SiC power devices and modules are suitable for the high power condition requirement, at the same time, the switching loss and the system volume have been reduced by more than half. However, the domestic research in SiC power MOSFET devices is still at a primary stage and there are significant gaps compared with the international level. This thesis contains the design, optimization, layout and experiment of 1700 V SiC DMOS device on account of the actual process conditions of domestic research institutes. The experimental results were tested and analyzed which can offer theoretical support and technical guidance for the application of 1700 V SiC DMOS.In this thesis, the cell parameters of 1700 V 4H-Si C DMOS are designed by Atlas which is the device simulating module of Silvaco firstly. The gate oxide thickness, the JFET region width, the channel length and the P_base doping profile are optimized considering the trade-off of the breakdown voltage, threshold voltage and on resistance. When the parameters of the cell have been fixed, the effect of field plate(FP), single-etched junction termination extension(JTE) and field limiting ring(FLR) to the breakdown voltage is investigated in consideration of curvature effect. In addition, based on the Fowler-Nordheim tunneling mechanism, the reliability of MOS device gate with a composite structure in SiO2 and HfO2 is investigated.Then, the quality of the interface characterization of the 4H-SiC MOS capacitance through 1300℃ high temperature oxidation and NO annealing has been investigated. It turns out that the interface states density can be decreased by high temperature oxidation and NO annealing. At last, the 1700 V 4H-SiC DMOS layout is designed by L-edit based on the present process conditions and the analysis of the experimental results has been completed. The breakdown voltage of 4H-SiC DMOS attains 2500 V and the threshold voltage reaches 4.8V, which provides a strong support for commercial production of 1700 SiC DMOS.