High-efficiency Microwave And Millimeter Wave Amplifier Research

In this paper, a miniaturized high efficiency Doherty power amplifiers based with an integrated directional coupler and millimeter-wave monolithic integrated power amplifier based on Ga As using PHEMT device are studied. Doherty power amplifier has the advantage of relatively high efficiency, good linearity advantages, easy to implement, simple circuit structure, low cost. Millimeter-wave monolithic integrated circuits are widely sued in millimeter-wave communication systems which play a vital role, especially in military electronic weapons systems and radar reconnaissance system. High efficiency microwave and millimeter wave amplifier are studied and designed, the main contents are as follows.This paper attempts to design the miniaturization of high-efficiency design using an integrated directional coupler playing power dividers and phase compensation and adjustment effects instead of conventional quarter-wavelength phase adjustment line of Doherty amplifier. Also, directional coupler can. reduce the amplifier’s dimensions at the same time. The Doherty amplifier successfully achieves the gain more than 14 d B with the gain fluctuation about 0.4 d B and 1d B compression power of 44 d Bm PAE is more than 30% respectively for 10 d B output power back off at the work frequency 2580-2610 MHz. Good agreement between the simulated and measured results can be observed.ka-band millimeter-wave high-efficiency amplifiers is designed based on Ga As process. We analysis of the design of the basic theory of monolithic integrated amplifier, and component selection, and circuit topology selection. Harmonic Optimization is used for high efficiency harmonic ka-band monolithic amplifier integrated amplifier. Design specifications of Ka-band millimeter-wave high-efficiency amplifier designed in this paper are as follows: Frequency range: 27 ~ 28 GHz, the output of power≥22 d Bm, PAE ≥40 %, power gain ≥30d B, band gain flatness ≤ ± 1 d B, saturation power band flatness ≤ ± 0.5 d B, the chip area ≤1.5 mm × 2.3 mm.