Research And Design Of The High Efficiency Doherty Power Amplifier

In order to ameliorate the utilization and throughput of spectrum,currently 4G LTE and 5G mobile communications technologies are both adopting a linear modulation scheme with non-constant envelope,with the latter still in the stage of laboratory research and its core being the multi-antenna technology.The index of linearity determines the efficiency of the non-constant envelop.Due to their opening characteristic and dissipation function,traditional power amplifiers can achieve the highest efficiency only at their maximum power,but with the regression of their output power,their efficiency rapidly decays.In practice,due to the difference in the communication distance,a power amplifier needs to work in a variety of back-off states,which poses a great challenge to its efficiency.The energy consumption of the power amplifier is the largest in the whole RF system and its efficiency is the main bottleneck in reducing the operating costs and improving the reliability of the system.As a result,linearity and efficiency are the key points in the current research.Because of its simple structure,low costs and easy implementation,the Doherty power amplifier has gradually become the mainstream efficiency enhancement technology.This thesis consists of six chapters.First paragraph is the preface.The second chapter describes the general indicators of the power amplifier and the traditional mode of operation.The third chapter mainly describes the working principles of the Doherty power amplifier circuit.The fourth chapter demonstrates the design process and simulation results of a Doherty power amplifier with an ADS platform and MRF7S21110 HRS LDMOS Freescale model.The fifth chapter is simulation optimization and measurement.The sixth chapter is the conclusion of the whole paper.A power amplifier for LTE downlink from 2110 MHz to 2170 MHz designed,tested with iterations of simulation and optimized.The power amplifier has a gain of 16 dB,PAE of 49%,and an IMD3 of-25.1 dBc,with a small decrease in linearity achieving great improvement in efficiency.Finally,the circuit layout is drawn with lincal and on PADS platform,and printed out.