Testing, Modeling, And Simulation Of Novel Nanowire Device

When the Nanowire device gets into the Nanowire scale, their 3-D structure could be more beneficial for area reduction, and realize its function in more less area. Among the Nanowire-scale devices, the application for MOSFET devices is widely used. This paper is mainly using the Nanowire device, which is made in Nano Facility Center,National Chiao Tung University, and the layout is designed by Professor Horng-Chih Lin. The performance of the Nanowire device is consistent with normal MOSFET,namely the current of Nanowire FET is controlled by gate voltage, by changing the gate voltage, we can control the on-off state of the Nanowire device. The channel of the Nanowire device is made of implanted Si, and its structure is quadruple gate. This paper is mainly for the the testing, modeling and simulation of the Nanowire device made in National Chiao Tung University.For the testing, we study on the I-V characteristic and ESD characteristic. I-V characteristic test result shows, the electronic characteristic of Nanowire MOSFET device is like the electronic characteristic of normal MOSFET, but the drain current for the Nanowire device is much lower, and in high temperature, the device could run into three states, including high current steady state, performance attenuation and performance turbulence. For the ESD test, after the ESD TLP test, we can get, the Vt2 for triangular channel is much larger than the Vt2 of rectangular channel, and for the same shape Nanowire device, the larger the channel’s area, the larger the Vt2. And the It2 for triangular channel is much larger than the It2 of rectangular channel, the larger the channel’s area, the larger the It2.For the modeling, we use the latest model BSIM CMG proposed by the BSIM research group, University of California, Berkeley. The modeling BSIM CMG applies for the nanowire scale devices. This paper introduces the drain current model, intrinsic capacitance model and threshold model of the BSIM CMG. After the extraction of the parameters of the Nanowire device, we use Hspice for the simulation of the electronic characteristic of the Nanowire device, to test the curves of Id-Vg and Id-Vd. Comparing the modeling results with the test result, we can get that the BSIM CMG model applies for the devices in this paper, and the deviation is within acception.For the simulation, we use sentaurus to get the simulation results in this paper. Byusing the device structure and the implantation concentration of the drain, source and gate, we can get the simulation of the Nanowire MOSFET device. The structure for the nanowire device is three dimensional device, the process parameter, the size are according to the process parameters, the threshold voltage, electronic characteristic and testing result are consistent with test result. For the modeling, the threshold is the same as the test result, and when the device turns on, the drain current changes exponentially with gate voltage. For the drain voltage, when the gate improves, the drain current improves, just like the trend of test result. The simulation result verifies the effectiveness of the hspice simulation, and could be used in the future design of the Nanowire device design.